FS450, FS451
i-Net TV InterfaceVideo Processor
Features
has a programmable down scaler to fit the
incoming resolution to the output display format.The CCIR 656 ports allow external interface toother video chips. The sync control block
generates frame reset for genlocking other videocomponents. Required external components areminimal: a single 27 MHz oscillator or crystaland passive parts.
Digital progressive RGB inputs are downscaled orupscaled to the CCIR-656 horizontal pixel countand converted to the 656 format. Vertical scalingand flicker filtering are done in 656 format.The Flicker Filter is an advanced 2 dimensionalfilter that enhances text quality. Flicker Filter andSharpness parameters are programmable.A digital video encoder that generates analog Y/Cand Composite Video outputs is part of theFS450. For the composite output in NTSC, Y-Notch and C-Bandpass filters are available. ForRGB and YUV outputs, the encoder may bebypassed via a YUV to RGB transcoder forSCART compatible video.
Scaling and clock parameters are automaticallyprogrammed by the driver, so the system remainsgenlocked with resolution changes. The inputparameters to the automatic scaling are TV
viewable area, PAL or NTSC, and the GCC CRTControl Registers’ settings.
The FS451's encoder incorporates Macrovision 7anti-copy protection technology.
All parameters can be read and written via the I2Ccompatible serial port.
Power is derived from +3.3V digital and analogsupplies. The package is 100-lead Quad FlatPack (PQFP).
•
Flexible clock, data, and electrical interfacesallows glue-less digital interface to Intel82810, National Geode and most othergraphic controller chips (\"GCC\")
• Capable of operating as clock master,
pseudo-master, and slave and supports bothsingle and differential master clocks• Programmable 2D scaling †
– Variable horizontal up and down scale– Variable vertical downscale
– Output format can be tuned to the exact
dimensions of the TV• Advanced 2-D flicker filter †
• Supports Multiple Progressive Input
Resolutions
– 0x480 to 1024x768• Multiple Output Standards
– NTSC, NTSC-EIAJ, PAL-B/D/G/H/I/M/N– Composite, S-Video, RGB SCART– Composite Y-Notch and C-Bandpass
Filters
• Genlock the GCC and incoming Video– Provides the pixel clock to the GCC
generated from a single 27MHz clock– Provides frame synchronization output
signal for other video components• CCIR 656 outputs
• CCIR 656 input to the encoder• 10-bit output D/A converters
• Macrovision 7 compliant (FS451 only)• I2C‡ compatible port controls• High level programming interface• 100 pin PQFP package• 3.3V operation
†Note: Covered under US Patent # 5,862,268 and/orpatents pending.
‡
Note: I2C is a registered trademark of Philips Corporation.The FS450 SIO bus is similar but not identical to Philips I2Cbus.
Applications
Description
The i-Net TV FS450 is a fourth generation videoscan converter. It accepts many input
resolutions, rates and formats and converts themto NTSC or PAL standards compliant with
SMPTE-170M and CCIR-656 standards. The chip
JUNE, 2000, VERSION 1.2
1
• • • • • •
Internet Set Top Boxes
PC video out (TV Ready PCs)Cable/DVD Player Set Top BoxesWeb Appliances
Information AppliancesVideo Kiosks
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Typical System Architectural Block Diagram
OSCDVD656Synch ControlVGASynchsYUV toRGBDACsGCC ChipRGBColor SpaceConverterHorz and VerticalDown ScalerFlickerFilter656EncoderCompositeand Y/CVGA PixelClockPLLFS450Figure 1: Typical System Block Diagram
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1. Table of Contents, Figures & Tables
1.2.
Table of Contents, Figures & Tables3Architectural Overview52.1Oscillators and PLLs...........................52.2Serial Control Port...............................62.3Sync Control.......................................62.4Input and Output Frame Formats..........62.5Color Space Converter and Scaler.........72.6Flicker Filter........................................72.7Encoder..............................................72.8YUV to RGB Converter.........................7Typical System Configurations83.1GCC ⇒ TV Output Only.......................83.2GCC or DVD Output Switched ⇒ TV.....93.3Multiple Digital Video Sources Blended
⇒ TV...............................................10Pin Assignments114.1FS450 ⇔ GCC Pin Mapping...............12Pin Descriptions13Control Register Definitions166.1Control Register Map.........................166.2Control Register Definitions................206.2.1IHO - Input Horizontal Offset......206.2.2IVO - Input Vertical Offset..........206.2.3IHW - Input Horizontal Width.....216.2.4VSC – Vertical Scaling Coefficient216.2.5HDSC, HUSC – Horizontal
Down/Up Scaling Coefficients....22
6.2.6CR - Command Register...........236.2.7SP - Status Port.......................256.2.8NCON - Numerator of NCO Word266.2.9NCOD - Denominator of NCO Word
...............................................27
6.2.10APO, ALO, AFO - Auxiliary Pixel,
Line, and Field Offsets..............28
6.2.11HSOUTWID, HSOUTST,
HSOUTEND - HSync Out Width,Starting and Ending Edge..........29
6.2.12SHP, FLK - Sharpness and Flicker
Filter.......................................32
6.2.13REV - Revision Number.............336.2.14MISC - Miscellaneous Bits 34, 35
Register...................................34
6.2.15FIFOL, FIFOH - FIFO Status Port
Full/Empty...............................35
6.2.16FFO_LAT - FIFO Latency..........356.2.17VSOUTWID, VSOUTST,
VSOUTEND - VSync Out Width,Starting and Ending Edge..........36
6.2.18CHR_FREQ - Chroma Subcarrier
Frequency...............................37
6.2.19Chroma Phase, Miscellaneous Bits
45...........................................38
6.2.20Miscellaneous Bits Registers 46
and 47.....................................39
6.2.21HSync Width (48), Burst Width
(49).........................................40
6.2.22Back Porch Width (4A), Cb Burst
Amplitude (4B).........................40
6.2.23Cr Burst Amplitude (4C),
Miscellaneous Bits Register 4D.41
6.2.24Black Level (4E).......................416.2.25Blank Level (50)........................426.2.26Number of Lines (57-58)............426.2.27White Level (5E).......................436.2.28Cb Color Saturation (60)............436.2.29Cr Color Saturation (62).............436.2.30Tint (65)...................................446.2.31Width of Breezeway (69)...........446.2.32Front Porch (6C).......................446.2.33Active Video Line (71-72), First
Video Line (73).........................45
6.2.34Miscellaneous Bits 74, Sync Level
(75).........................................46
6.2.35VBI Blank Level (7C).................476.2.36SOFT_RST, ENC_VER - Encoder
Soft Reset, Encoder Version.....47
6.2.37Misc. Bit Reg. 80, WSS Clock (81-82), WSS Data F1(83-85)..........48
6.2.38WSS Data Field 0(86-88), WSS
Line Number Field 1 ()...........49
6.2.39WSS Field 0 Line Number, WSS
Level, Misc. Bits Reg. 8D (8A-8D)50
7.Design and Layout Considerations527.1Pixel Phase Lock Loop......................527.2Video Output Filters...........................527.3Analog Power Supply Bypassing,
Filtering, and Isolation........................527.4Power and Ground.............................527.5Interfacing to the FS450 in a Mixed
Voltage Environment..........................537.5.1Interfacing to the SIO bus..........538.Specifications558.1Absolute Maximum and Recommended
Ratings.............................................558.2Electrical Characteristics...................568.3Switching Characteristics...................579.Mechanical Dimensions5.1100-Lead PQFP (KH) Package...........5810.Revision History5911.Order Information59
3.
4.5.
6.
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Figure 1: Typical System Block Diagram................2Figure 2: FS450 Functional Block Diagram.............5Figure 3: GCC Frame Format................................6Figure 4: CCIR 601/656 Field Format......................7Figure 5: GCC ⇒ TV Output Only..........................8Figure 6: GCC or DVD output switched ⇒ TV.........9Figure 7: Multiple digital video sources blended
⇒ TV.........................................................10Figure 8: CCIR 656 Timing Block Diagram............30Figure 9: Auxiliary NTSC Reference Signals..........31Figure 10: Auxiliary PAL Reference Signals..........31Figure 11. SIO Translation Using Long-tail
Resistors D1 = 1N4148................................53Figure 12. SIO Translation Using Current Mirrors
D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904....Figure 13: Package Outline & Dimensions............58
Table 1: FS45x Pin Assignments.........................11Table 2: FS450 to GCC Pin Mapping....................12Table 3: SAV and EAV Control Words..................24Table 4: GCC Port Mapping (UIM_MOD)...............24Table 5: NCO_LOAD Control Bits.........................34Table 6: NOTCH_FRQ Values..............................50Table 7: Typical Register Values for Various
Standards...................................................51
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2. Architectural Overview
The FS450 i-Net TV Video Interface Processor provides NTSC or PAL TV out for Intel's 82810 Video Co-processor and many other 3D graphic controller (\"GCC\") chips. It accepts digital RGB in, converts it toCCIR 656 digital video, provides interfaces to external 656 digital DVD systems, windowing hardware, alphablenders, et al and outputs very high quality RGB, YUV, S-Video, or Composite Video. The chip consists ofthe following major sections:
• • • •
REDGRNBLUEREDEGRNEBLUVSyncHSyncBlank
Oscillators and PLLsSerial Control PortSync Control
Input and Output Frame Formats
Universal Input Mux& Prescaler• • • • Color Space Converter & ScalerFlicker FilterEncoder
YUV to RGB Converter
/12/24 H/24Cache/24/6RGBtoYUV CCIR656Formatter/16 VFlicker/16/32FilterFIFO/32 H/16/8CCIR656Out
/3/3VGATimingGeneratorYUVtoRGB/16CCIR 656TimingGenerator/30Multiplexer/2HBlank OutVBlank OutField OutAuxiliaryHREFVREF/10/10/10DACDACDACCCIR656InRED/LUMAGRN/CVBSBLU/CHRMADemux/8 HEncoder/30HBlank InVBlank InField In/3Decoder27 MHzClock
NCODividero wVCO CPUVGAClock
DividerFigure 2: FS450 Functional Block Diagram
2.1 Oscillators and PLLs
The FS450 synthesizes a 27 to 85 MHz clock off of the 27 MHz Television clock and supplies this clock(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous tothe RGB data and Sync information. This clock has a 1½ Hz resolution and must be adjusted so the GCCscaled input data rate exactly matches the CCIR 656 data output rate.
The VG_CKOUT Phase Lock Loop (PLL) synthesizer uses Numerically Controlled Oscillator (NCO) to fineadjust the 27MHz oscillator to a clock precisely matched to the digital RGB data coming from the GCC.Additionally, the PLL itself can be controlled by programming the numerator (M) and denominator (N) of thePLL itself. The combination of the PLL synthesizer and NCO are used to precisely match the input to theoutput.
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2.2 Serial Control Port
FS450 setup is programmed by registers that are accessible via the I2C‡ compatible serial port (SIO).Status and Revision ID can also be read from the registers.
‡
Note: I2C is a registered trademark of Philips Corporation. The FS450 SIO bus is similar but not identicalto Philips I2C bus.
2.3 Sync Control
The FS450 operates in a slave mode, pseudo-master mode or full master mode. In pseudo-master mode,the GCC graphic controller derives the VGA pixel clock, horizontal sync, and vertical sync from
VGA_CLKOUT supplied by the FS450. The syncs are used inside the FS450 to capture the computer videoand are regenerated to supply to external devices such as genlocked video from a DVD player or tuner. Infull master mode, the FS450 supplies to the GCC horizontal and vertical sync in addition to the VGA pixelclock.
2.4 Input and Output Frame Formats
The FS450 does not contain a frame memory. Therefore, the FS450 output frame rate must be
synchronous to the input frame rate. To accomplish this, the active video portion in the output stream mustoverlay the corresponding active video time in the input stream. Several registers on the FS450 control thistiming as illustrated in the following figures:
VGA_HSYNC
IHO
VGA_VSYNCIVOC
A
BlankBlankBlank
D
IVO + IVW
BlankBlank
BlankBlackBlackBlackBlank
BlankBlackActive Video
BlackBlank
BBlankBlackBlackBlackBlank
IHO + IHWBlankBlankBlankBlankBlank
Figure 3: GCC Frame Format
IHO = OHO / HscaleIHW = OHW / Hscale
IVO = OVO / VscaleIVW = OVW / Vscale
The output frame timing is determined by the CCIR601 and 656 specifications. Input parameters IHO, IVO,and IHW must be set correctly so that when the image is scaled to the 656 output frame, the timingrequirements are met. Parameters A, B, C, and D are determined by the amount of underscan the userwants on the target television screen.
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656_HSYNC
OHO
656_VSYNCOVOC^
A^
BlankBlankBlank
D^
OVO + OVW
BlankBlank
BlankBlackBlackBlackBlank
BlankBlackActive Video
BlackBlank
B^
OHO + OHW
BlankBlackBlackBlackBlank
Figure 4: CCIR 601/656 Field Format
OHO = 139 NTSC, 145 PALOHW = 720
OVO = 20 NTSC, 23 PALOVW = 487 NTSC, 576 PAL
2.5 Color Space Converter and Scaler
The digital RGB from the GCC is horizontally compressed, stored into a line buffer cache. As the data ispulled from the line buffer cache, it is converted to 656 YUV and compressed vertically.
2.6 Flicker Filter
The FS450 flicker filter provides significantly more control over the display characteristics than a typical 3line average flicker filter. The FS450's flicker filter consists of both horizontal (Sharpness) and vertical(Flicker) controls. Thus, it is called a 2D flicker filter. Both the Sharpness and Flicker registers can be
programmed over a wide range to allow the user to tradeoff flicker and sharpness for readability and reducedeye fatigue.
2.7 Encoder
The FS450 contains a high quality 2x oversampled video encoder. The 656 luma information is up-sampledfrom 13.5 MHz sample rate to 27 MHz with a 19 tap filter which offers excellent flatness to 6MHz and 50 dBimage aliasing suppression. Chrominance information is up-sampled from 6.75MHz sample rate to 27 MHzwith four user selectable bandwidths. The encoder has programmable width and frequency luma notch filter.The encoder subcarrier is programmable in frequency and phase and with the independence of color format,vsync, and number of lines allows for the support of the many video standards, including all South Americanvariations. The FS450 video encoder outputs NTSC M, J and PAL B, D, G, H, I, M, N, Combination Nformats with 10 bits of resolution. Both Composite and S-Video outputs are available simultaneously.
2.8 YUV to RGB Converter
As an alternative to encoded PAL or NTSC, the user may select analog RGB outputs. Each channel ofRGB has 10 bits of resolution.
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3. Typical System Configurations
There are 3 \"typical\" system configurations envisioned for the FS450:
1) GCC ⇒ TV output only;
2) GCC or DVD output switched ⇒ TV;3) Multiple digital video sources blended ⇒ TV.
3.1 GCC ⇒ TV Output Only
27 MHzOSCSynchControlVGASynchsColor SpaceConverterHorz andDownVerticalScalerYUV toRGBDACsGCCRGBFlickerFilterEncoderCompositeand Y/CVGA PixelClockPLLFS450Figure 5: GCC ⇒ TV Output Only
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3.2 GCC or DVD Output Switched ⇒ TV
OSCDVD656Synch ControlVGA SynchsYUV toRGBDACsGCCRGBColor SpaceConverterHorz and VerticalDown ScalerFlickerFilter656EncoderCompositeand Y/CVGA PixelClockPLLFS450Figure 6: GCC or DVD output switched ⇒ TV
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3.3 Multiple Digital Video Sources Blended ⇒ TV
MPEG2DecoderCCIR 656VideoDecoderCCIR 656Video SyncsFrameMemoryCCIR 656OutputControlCCIR 656AlphaBlend27 MHz Decoder ClkCCIR65627 MHz Encoder ClkCrystalOscSync ControlVGA SyncsCCIR656YUV toRGBRGBDACsVGAControllerRGBColor SpaceConverterHorz and VerticalDown ScalerFlickerFilterEncoderCompositeand Y/CVGA Clk InVGA Clk OutNCOandPLLHoustonFigure 7: Multiple digital video sources blended ⇒ TV
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4. Pin Assignments
8081515010013031Pin1. 2. 3. 4. 5. 6. 7. 8. 9.
RORRGNRRR
NameTV_CKINXTALVDDOSCVSSOSC
Reserved (GND)Reserved (open)VSSDAVREFRREFVDDDACBYPASSY/RedVDDDAVSSDA
CVBS/GreenVDDDAC/BlueVDDDACSYNC
Reserved (open)Reserved (open)VDDPASCLKSDATASA10/7SA0VSSPARESET
Reserved (GND)Reserved (GND)
Pin31. P32. R33. R34. O35. O36. S37. O38. R39. O40. O41. O42. O43. O44. R45. R46. R47. R48. R49. R50. R
NameVGA_CKOUTVSSVDD
Reserved (open)Reserved (open)E5E4VSS
VGA_CKOUTTLE3E2E1E0BLANKVDD
VSYNC_INHSYNC_INP0P1VSS
Pin51. R52. R53. R. R55. R56. R57. R58. R59. R60. R61. R62. R63. R. R65. R66. R67. O68. O69. O70. R71. O72. O73. O74. R75. O76. O77. O78. R79. O80. O
NameP2P3P4P5
GTL_REFVDDP6P7P8P9VSSP10P11
VGA_NCKINVGA_PCKINVDDAVREFVSYNC_OUTAHREFVSS
HSYNC_OUTFIELD_OUTVBNK_OUTVDD
HBNK_OUTV656_OUT0V656_OUT1VSS
V656_OUT2V656_OUT3
Pin81. O82. R83. O84. O85. O86. R87. S88. S. S90. R91. S92. S93. S94. S95. R96. S97. S98. S99. S100. N
NameV656_OUT4VDD
V656_OUT5V656_OUT6V656_OUT7VSSFIELD_INVBNK_INHBNK_INVDDV656_IN0V656_IN1V656_IN2V656_IN3VSSV656_IN4V656_IN5V656_IN6V656_IN7
Reserved (open)
10. R11. R12. O13. R14. R15. O16. R17. O18. R19. O20. N21. N22. R23. R24. R25. R26. R27. R28. R29. G30. G
Table 1: FS45x Pin Assignments
R = Signal Required
O = Signal if used, else no connectS = Signal if used, else ground
G = Always GroundN = Always No Connect
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4.1 FS450 ⇔ GCC Pin Mapping
The following table maps the FS450/1 pins to the host GCC controller chip. Please contact your FOCUSrepresentative to obtain the most up-to-date reference schematics before initiating a design.FS450Pin #
FS450/1Pin Name
Intel82810
Pin NameUIM_MOD=0
TVCLKIN
TVCLK
CLKOUT0CLKOUT1TVHSYNCTVVSYNC
FP_CLK
FP_HSYNC_OUTFP_VSYNC_OUT
NationalCx5530MediaGXUIM_MOD=3nVidiaRiva TNTPin NameUIM_MOD=1S3
SavagePin NameUIM_MOD=1
3139674671684448495152535758596062634342414037362324
VGA_CKOUT
VGA_CKOUTTL
TVCLKINTVCLKOUT
TVCLKTVCLKRTVHSTVVS
VGA_PCKINVGA_NCKINHSYNC_INVSYNC_INHSYNC_OUTVSYNC_OUTBLANKP0P1P2P3P4P5P6P7P8P9P10P11E0E1E2E3E4E5SCLKSDATA
TVHSYNCTVVSYNC
BLANKLTVDATA0LTVDATA1LTVDATA2LTVDATA3LTVDATA4LTVDATA5LTVDATA6LTVDATA7LTVDATA8LTVDATA9LTVDATA10LTVDATA11
FP_DATA6FP_DATA7FP_DATA8FP_DATA9FP_DATA10FP_DATA11FP_DATA12FP_DATA13FP_DATA14FP_DATA15FP_DATA16FP_DATA17FP_DATA0FP_DATA1FP_DATA2FP_DATA3FP_DATA4FP_DATA5
LTVCLLTVDA
DDC_SCLDDC_SDA
SPSCLSPSDA
SPCLK1SPD1
TVD0TVD1TVD2TVD3TVD4TVD5TVD6TVD7TVD8TVD9TVD10TVD11
BLANKTVDAT0TVDAT1TVDAT2TVDAT3TVDAT4TVDAT5TVDAT6TVDAT7TVDAT8TVDAT9TVDAT10TVDAT11
Table 2: FS450 to GCC Pin Mapping
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5. Pin Descriptions
PinNameClocks
VGA_CKOUT
VGA_CKOUTTL
PinNumber313965
Type/ValuePin Function Description
GTLP output(open drain)LVTTL outputGTLP input
VGA_PCKIN
VGA_NCKINGTLP input
TV_CKINXTALHSYNC_OUTVSYNC_OUT
127168
LVTTL inputLVTTL outputLVTTL outputLVTTL output
VGA Clock Output. Clock to GCC TVCLKIN. Synthesizedfrom TV_CKIN. 27 to 85 MHz range.
VGA Clock Output. Clock to GCC TVCLKIN. Synthesizedfrom TV_CKIN. 27 to 85 MHz range.
VGA Clock Input Positive Edge. Clock from GCC
CLKOUT, buffered form of VGA_CKOUT. Used to latch risingedge RGB data.
VGA Clock Input Negative Edge. Clock from GCCCLKOUT, buffered form of VGA_CKOUT. Used to latchnegative edge RGB data.
Television Clock Input. Clock for the CCIR 656 I/O and thevideo encoder. 27 MHz.
Television Clock XTAL Output. Buffered version ofTV_CKIN. For use with a 27 MHz crystal.
HSYNC Output. Output from FS450 to GCC to support slavemode operation.
VSYNC Output. Output from FS450 to GCC to support slavemode operation.
Reset. Active Low. Resets internal state machines andinitializes default register values.Reserved Inputs. Connect to VSS.Reserved Outputs. Do not connect.
Global Controls and Reserved PinsRESET28TTL input
(pull down)
Reserved5,29,30TTL input
(ground)
Reserved6,20,21,LVTTL output
34,35,100(leave open)
Digital RGB InputsP11-P063,62,60,5GTLP input
9,58,57,,53,52,51,49,48
E5-E036,37,40,4GTLP input
1,42,43
GTL_REF55GTLP REFHSYNC_INVSYNC_INBLANK
4744
GTLP inputGTLP inputGTLP input
Digital GTLP port input. Digital video input, multiplexed ornon-multiplexed. Connects to GCC's digital video out.
Digital GTLP port input. Non-multiplexed extended digitalvideo input. Connects to GCC's digital video out.
Digital GTLP Reference input. Voltage threshold referencefor GTLP inputs. Reference is 1.0 volts.
Digital HSYNC VGA input. Connects to GCC TVHSYNC.Digital VSYNC VGA input. Connects to GCC TVVSYNC.Digital BLANK VGA input. True outside of GCC activearea. Connects to GCC BLANK#.
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PinName
Video OutputsY/Red
PinNumber12
Type/ValuePin Function Description
analog video
CVBS/Green15analog video
C/Blue17analog video
CSYNC19LVTTL output
Video output. As programmed by Command RegisterOFMT bit:
0 Luminance component Y of S-video.1 Red component of RGB.
Video output. As programmed by Command Register OFMTbit:
0 Composite video.
1 Green component of RGB.
Video output. As programmed by Command Register OFMTbit:
0 Chrominance component of S-video.1 Blue component of RGB.
Composite sync output. Active high digital composite syncfor SCART video outputs.
Voltage reference input/output. If unconnected, except fora 0.1µF capacitor to ground for noise decoupling, the internal1.276 Volt band-gap reference will be supplied to the threeD/A Converters. An external 1.276 Volt reference connectedto the VREF pin, will override the internal voltage reference.Reference resistor. Connected between RREF and ground,this resistor sets the current range of the D/A converters.Use 390Ω for a 37.5Ω load and 780Ω for a 75Ω load.
Bypass Capacitor. A 0.1µF capacitor must be connectedbetween CBYPR and VDDDA to reduce noise at the D/Aoutputs.
Digital CCIR 656 port input. 8 bits wide. Y, Cr, Cbmultiplexed digital input port
Digital TV Horizontal Blank input. Horizontal Blank for usewith the V656_IN ports.
Digital TV Vertical Blank input. Vertical Blank for use withthe V656_IN ports.
Digital TV Field input. Field bit for use with the V656_INports.
Voltage ReferenceVREF8
+1.276 V
RREFCBYPASS
9390/780Ω
110.1 µF
CCIR 656 Input PortV656_IN7-099,98,97,9TTL input
6,94,93,92(pull down)
,91
HBNK_INTTL input
(pull down)
VBNK_IN88TTL input
(pull down)
FIELD_IN87TTL input
(pull down)
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PinPinType/ValueNameNumberCCIR 656 Output PortV656_OUT7-085,84,83,8LVTTL output
1,80,79,77
,76
HBNK_OUT75LVTTL outputVBNK_OUTFIELD_OUTAHREF
737269
LVTTL outputLVTTL outputLVTTL output
Pin Function Description
Digital CCIR 656 port output. 8 bits wide. Y, Cr, Cb
multiplexed digital output port
Digital TV Horizontal Blank output. Horizontal Blank foruse with the V656_OUT ports.
Digital TV Vertical Blank output. Vertical Blank for usewith the V656_OUT ports.
Digital TV Field output. Field bit for use with the V656_OUTports.
Digital Auxiliary Horizontal Reference output. HorizontalSync for external hardware. Programmable advance orretard.
Digital Auxiliary Vertical Reference output. Vertical Syncfor external hardware. Programmable advance or retard.Serial address length select. Selects the length of theserial address:
SA10/7 = H: 10-bitsSA10/7 = L: 7-bits
Serial data address bit 0. . Selects the serial bus address:SA0 = H: 0x6A, 276SA0 = L: 0x4A, 224
Serial data. Data line of the serial port. Connect to GCCLTVDA.
Serial clock. Clock line of the serial port. Connect to GCCLTVCL.
VGA_CKOUT Phase-locked loop Power. Filtered +3.3 voltpower for VGA_CKOUT phase locked loop.
TV Crystal Oscillator Power. Filtered +3.3 volt power forTV XTAL oscillator.
Digital Power. 3.3 volt power for digital section of chip.D/A Converter Power. Filtered +3.3 volt power for 10 bitvideo D/A converters.
VGA_CKOUT phase-locked loop ground.TV Crystal Oscillator ground.
Digital ground. +3.3 volt power return.
AVREFSerial PortSA10/7
67LVTTL output
25
TTL input(pull down)
SA0SDATASCLK
26
TTL input(pull down)TTL I/0
(open drain)TTL Input
2423
Power and GroundVDDPA22VDDOSCVDDVDDDAVSSPAVSSOSCVSSVSSDA333,45,56,66,74,82,9010,13,16,1
8274
32,38,50,61,70,78,86
,957,14
+3.3 V+3.3 V+3.3 V+3.3 V0 V0 V0 V
0 VD/A Converter Ground.
JUNE, 2000, VERSION 1.215COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6. Control Register Definitions
6.1 Control Register Map
FunctionReg.Bit #NameTypeInput Horizontal Offset07-0IHO7-0R/W12-0IHO10-8R/WInput Vertical Offset27-0IVO7-0R/W32-0IVO10-8R/WInput Horizontal Width47-0IHW7-0R/W51-0IHW9-8R/WVertical Scaling Coefficient67-0VSC7-0R/W77-0VSC15-8R/W
Horizontal Down/Up Scaling Coefficients87-0HDSC7-0R/W (Down)97-0HUSC7-0R/W (Up)Command RegisterC7-0CR7-0R/WD7-0CR15-8R/WStatus PortE7-0SP7-0RF--RNumerator of NCO Low Word107-0NCON7-0R/W117-0NCON15-8R/WNumerator of NCO High Word127-0NCON23-16R/W13--Denominator of NCO Low Word147-0NCOD7-0R/W157-0NCOD15-8R/WDenominator of NCO High Word167-0NCOD23-16R/W17--Auxiliary Pixel Offset187-0APO7-0R/W191-0APO9-8R/WAuxiliary Line Offset1A6-0ALO6-0R/W1B--R/WAuxiliary Field Offset1C0AFOR/W1D--HSync Pulse Width1E7-0HSOUTWID7-0R/W1F2-0HSOUTWID10-8R/W
JUNE, 2000, VERSION 1.2
16
Reset Value00
000000D0 (720.)020000000000100000
00 (131,072.)0002
00 (524,288.)0008
0000000000000000
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
FunctionReg.Bit #NameTypeHSync Starting Edge207-0HSOUTST7-0R/W212-0HSOUTST10-8R/WHSync Ending Edge227-0HSOUTEND7-0R/W232-0HSOUTEND10-8R/WFlicker Filter Sharpness244-0SHP4-0R/W25---Flicker Filter2-0FLK4-0R/W27---Part Revision327-0REV7-0R/W337-0REV15-8R/WMisc Register347-0MISC7-0R/W357-0MISC15-8R/W
FIFO Status Port Full/FIFO Status Port Empty367-0FIFOF7-0R/W377-0FIFOE7-0R/WFIFO Latency387-0FIFOL7-0R/W397-0FIFOL15-8R/WVSync Pulse Width3A7-0VSOUTWID7-0R/W3B2-0VSOUTWID10-8R/WVSync Starting Edge3C7-0VSOUTST7-0R/W3D2-0VSOUTST10-8R/WVSync Ending Edge3E7-0VSOUTEND7-0R/W3F2-0VSOUTEND10-8R/W
Reset Value00
000000000000000100008000000000000000000000
JUNE, 2000, VERSION 1.217COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
FunctionReg.Bit #NameTypeChroma Frequency
CHR_FREQ31-24R/W407-0
CHR_FREQ23-16R/W417-0
CHR_FREQ15-8R/W427-0
CHR_FREQ7-0437-0R/W
Chroma Phase, Miscellaneous Bits 45
CHR_PHASE7-0R/W447-0
451,0MISC45R/WMiscellaneous Bits 46, 47467-0MISC46R/W473-0MISC47R/WHSync Width, Burst Width
HSYNC_WID7-0R/W487-0
BURST_WID6-0R/W496-0
Backporch Width, CB Burst Level
BPORCH7-04A7-0R/WCB_BURST7-04B7-0R/W
CR Burst Level, Miscellaneous Bits 4D
CR_BURST7-04C7-0R/W
4D1-0MISC4DR/WBlack Level4E7-0BLACK_LVL9-2R/W4F1-0BLACK_LVL1-0R/WBlank Level507-0BLANK_LVL9-2R/W511-0BLANK_LVL1-0R/WNumber Lines
LINE_FRAME9-2R/W577-0
LINE_FRAME1-0R/W581-0
White Level5E7-0WHITE_LVL9-2R/W5F1-0WHITE_LVL1-0R/WCb Gain607-0CB_GAIN7-0R/W61--R/WCr Gain627-0CR_GAIN7-0R/W63--R/WChroma Tint Adjustment--R/W657-0TINT7-0R/WStatus Port68--R/W694-0BREEZE_WAY4-0R/WStatus Port6C5-0FRNT_PORCH5-0R/W6D--R/W
Reset Value21 (569,408,3.)
F07C1F000005007E (126.)44 (68.)76 (118.)3B (59.)000086 (282.)023C (240.)0083 (525.)01C8 (800.)0022 (137.)0122 (137.)01000000
16 (22.)20 (32.)00
JUNE, 2000, VERSION 1.218COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
FunctionReg.Bit #NameTypeReset ValueActiveLine
ACTIVELINE10-3R/W717-0B4 (1440.)ACTIVELINE2-0722-0R/W00
Chroma Phase
FIRST_LINE7-0737-0R/W15 (21.)
Miscellaneous Bits 74, Sync Level747-0MISC74R/W02757-0SYNC_LVL7-0R/W48 (72.)VBI Blank Level
VBIBLNK_LVL9-27C7-0R/W4A (296.)VBIBLNK_LVL1-07D1-0R/W00
Reset, Encoder Version7E0SOFT_RSTR/W17F7-0ENC_VER7-0R20Miscellaneous Bits 80, WSS Clock Frequency (upper)806-0MISC80R/W7817-0WSS_CLK11-4R/W2F (759.)WSS Clock Frequency (lower), WSS Data Field 1 (upper)823-0WSS_CLK3-0R/W07
WSS_DAT119-12R/W837-000
WSS Data Field 1 (lower)
WSS_DAT111-4R/W847-000
853-0WSS_DAT13-0R/W00WSS Data Field 0 (upper)
WSS_DAT019-12R/W867-000WSS_DAT011-4R/W877-000
WSS Data Field 0 (lower), WSS Line 1 Delay883-0WSS_DAT03-0R/W007-0WSS_LINF17-0R/W00WSS Level (lower)8A7-0WSS_LINF07-0R/W008B7-0WSS_LVL9-2R/WFF (1023.)WSS Level (upper), Miscellaneous Bits 8D8C1-0WSS_LVL1-0R/W038D4-0MISC8D4-0R/W00
JUNE, 2000, VERSION 1.219COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2 Control Register Definitions
In the following definitions, range is defined as:
{min value : [max value]}
Please note that registers 0-3F use the little endian numbering scheme while registers 40-8D usethe big endian numbering scheme.
6.2.1 IHO - Input Horizontal OffsetInput Horizontal Offset Low (0)
7IHO7
6IHO6
5IHO5
4IHO4
3IHO3
2IHO2
1IHO1
0IHO0
Input Horizontal Offset High (1)
70
60
50
40
30
2IHO10
1IHO9
0IHO8
Reg1, 0
Bit#2-0, 7-0
Bit NameIHO10-0
Description
Input horizontal offset bits [10-0]. Horizontal displacement of theimage in pixels from the leading edge of horizontal sync. IHO is anunsigned number.
Range: {0 : [Total Pixels/Line]-1}
6.2.2 IVO - Input Vertical OffsetInput Vertical Offset Low (2)
7IVO7
6IVO6
5IVO5
4IVO4
3IVO3
2IVO2
1IVO1
0IVO0
Input Vertical Offset High (3)
70
60
50
40
30
2IVO10
1IVO9
0IVO8
Reg3, 2
Bit#2-0, 7-0
Bit NameIVO10-0
Description
Input vertical offset bits [10:0]. Vertical displacement of the
image in lines from the leading edge of vertical sync plus a one linebias. IVO is an unsigned number.
Range: {0 : [Total Lines/Frame]-1}
JUNE, 2000, VERSION 1.2
20
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6.2.3 IHW - Input Horizontal WidthInput Horizontal Width Low (4)
7IHW7
6IHW6
5IHW5
4IHW4
3IHW3
2IHW2
1IHW1
0IHW0
Input Horizontal Width High (5)
70
60
50
40
30
20
1IHW9
0IHW8
Reg5, 4
Bit#1-0, 7-0
Bit NameIHW9-0
Description
Input horizontal width [9:0]. Total number of active VGA pixelsper line. IHW is an unsigned number.
Range: {0 : 970}
6.2.4 VSC – Vertical Scaling CoefficientVertical Scaling Coefficient (6)
7VSC7
6VSC6
5VSC5
4VSC4
3VSC3
2VSC2
1VSC1
0VSC0
Vertical Scaling Coefficient (7)
7VSC15
6VSC14
5VSC13
4VSC12
3VSC11
2VSC10
1VSC9
0VSC8
Reg7, 6
Bit#7-0
Bit NameVSC7-0
Description
Vertical scaling coefficient bits [15:0]. Vertical down scalingfactor = (1 + VSC/65,536). VSC is a two's complement number. IfVSC => 0, then the image is not effected.
Range: { [-32,769]:0}
JUNE, 2000, VERSION 1.221COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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6.2.5 HDSC, HUSC – Horizontal Down/Up Scaling CoefficientsHorizontal Down Coefficient (8)
7HDSC7
6HDSC6
5HDSC5
4HDSC4
3HDSC3
2HDSC2
1HDSC1
0HDSC0
Horizontal Up Coefficient (9)
7HUSC7
6HUSC6
5HUSC5
4HUSC4
3HUSC3
2HUSC2
1HUSC1
0HUSC0
Reg8
Bit#7-0
Bit NameHDSC7-0
Description
Horizontal down scaling coefficient bits [7:0]. Horizontal downscaling factor = (1 + VSC/128). HDSC is a two's complementnumber. If HDSC => 0, then the image is not effected.Horizontal up scaling coefficient bits [7:0]. Horizontal upscaling factor = (1 + VSC/128). HDSC is a two's complementnumber. If HDSC <= 0, then the image is not effected.
97-0HUSC7-0
HDSC Range: { [-63]:0 }HUSC Range: { 0:127 }
JUNE, 2000, VERSION 1.222COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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6.2.6 CR - Command RegisterCommand Register (C)
7FFO_CLR
6
CACQ_CLR
5LP_EN
4YCOFF
3COMPOFF
2NCO_EN
1CLKOFF
0SRESET
Command Register (D)
7UIM_MOD1RegCCC
6UIM_MOD0Bit#
012
50Bit NameSRESETCLKOFFNCO_EN
4UIM_DECDescription
Soft Reset. Resets the FS450.
Clock Off. Turns off FS450 clock to minimize power.
Enable NCO Latch. When this bit is set, transfers the NCO
words from the I2C registers into the NCO. The NCO synthesizesthe VGA clock from the 27MHz FS450 clock. This clock must beadjusted so the VGA scaled input data rate exactly matches theCCIR 656 data output rate.
Composite (CVBS) Output Off. Turns off the CVBS output D/A.SVideo (YC) Outputs Off. Turns off the YC output D/As.
Loop Through Enable. Enables the CCIR 656 data on the outputport to loop directly to the input port (no external routing).Counter Acquisition Flag Clear. Setting this bit clears theCounter Acquisition Flag.
FIFO Clear. Setting this bit clears the FIFO depth registers andthe FIFO State register.
CCIR 656 PAL or NTSC Input. Sets the number of lines writtenthrough the FIFO. When set, the number of lines is 576 for PAL,when clear, 487 lines for NTSC.
Standard or VMI 656 Input Control. Select standard (externalpins) horizontal/vertical blank and field codes or inserted CCIR601/656 SAV/EAV (Start/End Active Video) embedded codes.Output Format Control. Switches between RGB orComposite/YC output. When set, the output is RGB.
Universal Interface Mux Clock Mode. If set, input pixels areclocked in on the falling edge of the P and N input clocks. If clear,input pixels are clocked on the rising and falling edge of N clock.Universal Interface Mux Decimator. Turns on the horizontalprescaler divide by 2 to support XGA mode.
Universal Interface Mode Select. Selects the VGA interfacemode (see table below).
23
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PRELIMINARY INFORMATION
3UIM_CLK
2OFMT
1STD_VMI
0
NTSC_PALIN
CCCCCD
345670
COMPOFFYCOFFLP_EN
CACQ_CLR
FFO_CLR
NTSC_PALIN
D1STD_VMI
DD
23
OFMTUIM_CLK
DD
47,6
UIM_DEC
UIM_MOD1-0
JUNE, 2000, VERSION 1.2
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
Notes:
VMI 656 Input Control: If the Video Module Interface (VMI) mode is specified, SAV and EAV commands are
inserted into the CCIR601 data stream to coordinate down stream data processing. The SAV and EAV Controlwords have the following format:
YC DataPreamble CPreamble YStatus Word CStatus Word Y
D71001
D6100F
D5100V
D4100H
D3100P3
D2100P2
D1100P1
D0100P0
Table 3: SAV and EAV Control Words
F = 0 during field 1, F = 1 during field 2H = 0 for SAV, H = 1 for EAVV = 1 during vertical blanking
P3 = V xor HP2 = F xor HP1 = F xor V
P0 = F xor V xor H
UIM_MOD Mapping: The UIM_MOD (Universal Input Mux, UIM) bits select the mode for P0-P11 and E0-E5. The
intention is to support as many different 3D and GCC graphic controllers, CPU support chips and integratedCPUs as possible (collectively referred to in this data sheet as \"GCC\"). The following table shows the mappingin each mode for the digital RGB from the GCC to the appropriate port or extended port pin:UIM_MOD00111122333P/E PortM888DLM888DHM888ILM888IHM565ILM565IHM555LM555HN666N565N555
P11P10P9P8P7P6P5P4P3P2P1P0E5E4E3E2E1E0
G3G2G1G0B7B6B5B4B3B2B1B0XXXXXX
R7R6R5R4R3R2R1R0G7G5G4G3XXXXXX
G4G3G2B7B6B5B4B3G0B2B1B0XXXXXX
R7R6R5R4R3G7G6G5R2R1R0G1XXXXXX
G2G1G0B4B3B2B1B00000XXXXXX
R4R3R2R1R0G5G4G30000XXXXXX
G2G1G0B4B3B2B1B0XXXXXXXXXX
XR4R3R2R1R0G4G3XXXXXXXXXX
R5R4R3R2R1R0G5G4G3G2G1G0B5B4B3B2B1B0
R4R3R2R1R00G5G4G3G2G1G0B4B3B2B1B00
R4R3R2R1R00G4G3G2G1G00B4B3B2B1B00
Table 4: GCC Port Mapping (UIM_MOD)
1) All input bits are MSB justified
3) For GCC to P/E Mapping, see Table 2
2) Shaded modes require zero padding at input port
JUNE, 2000, VERSION 1.224COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.7 SP - Status PortStatus Port Low (E)
70
60
50
40
30
20
1FIFO_ST
0CACQ_ST
Status Port High (F)
70
60
50
40
30
20
10
00
RegEE
Bit#
01
Bit NameCACQ_STFIFO_ST
Description
Cache Status. Status of horizontal downscaler cache (=1 if overflowed).
FIFO Status. Output FIFO status (=1 if over/under flowed).
Notes:
FIFO Status:
FS450 does not have a frame memory. In FS450 the scaled input data rate and the output data rates are thesame. The FIFO takes up the slack during the asynchronous horizontal blanking interval of the input and output.The FIFO depth (1024) is only slightly larger that the 720 output pixels required to form a CCIR 601 data stream.The extra pixels are used for data overrun protection.
At the coincidence of a Filtered Horizontal and Vertical Start, the input and output FIFO pointers are reset to the tobeginning of the memory and data writes commence. Next, 24 output clock cycles after the Filtered Horizontal andVertical Start occur, the CCIR 656 Timing Generator issues a FIFO Horizontal and Vertical Start. This causes theHorizontal Upscaler to issue a TV read and the FIFO starts to read data.
If a data overrun occurs, the offending FIFO’s pointer is halted and black is output to the Horizontal Upscaler. Also,the FIFO data overrun flag is set.
JUNE, 2000, VERSION 1.225COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.8 NCON - Numerator of NCO WordNumerator of NCO Word (10)
7NCON7
6NCON6
5NCON5
4NCON4
3NCON3
2NCON2
1NCON1
0NCON0
Numerator of NCO Word (11)
7NCON15
6NCON14
5NCON13
4NCON12
3NCON11
2NCON10
1NCON9
0NCON8
Numerator of NCO Word (12)
7NCON23
6NCON22
5NCON21
4NCON20
3NCON19
2NCON18
1NCON17
0NCON16
Numerator of NCO Word (13)
70
60
50
40
30
20
10
00
Reg12, 11, 10
Bit#7-0,7-0,7-0
Bit NameNCON23-0
Description
Numerator of NCO Word [23:0]. Numerator of clock synthesizerto generate VGA input clock. NCON is a 24 bit unsigned number.
Range: {0 : NCOD/2}
The FS450 synthesizes a 27-85 MHz clock from the 27 MHz TV_CKIN and supplies this clock
(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous tothe RGB data and Sync information. This clock has a 1.5 Hz resolution and can be adjusted so the VGAscaled input data rate exactly matches the CCIR 656 data output rate.
Frequency VGA / Frequency 656 = # VGA Pixels / # 656 Pixels x # VGA Lines / # 656 Lines
Frequency VGA / Frequency 656 = NCON / NCOD x M / N
Example: for SVGA mode, typ. total pixels x lines ~ 1024 x 625; let M=512, N=128:
NTSC and PAL: NCON = 1024 x 625 = 0,000
JUNE, 2000, VERSION 1.226COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.9 NCOD - Denominator of NCO WordDenominator of NCO Word (14)
7NCOD7
6NCOD6
5NCOD5
4NCOD4
3NCOD3
2NCOD2
1NCOD1
0NCOD0
Denominator of NCO Word (15)
7NCOD15
6NCOD14
5NCOD13
4NCOD12
3NCOD11
2NCOD10
1NCOD9
0NCOD8
Denominator of NCO Word (16)
7NCOD23
6NCOD22
5NCOD21
4NCOD20
3NCOD19
2NCOD18
1NCOD17
0NCOD16
Denominator of NCO Word (17)
70
60
50
40
30
20
10
00
Reg16, 15, 14
Bit#7-0,7-0,7-0
Bit NameNCOD23-0
Description
Denominator of NCO Word [23:0]. Denominator of clocksynthesizer to generate VGA input clock. NCOD is a 24 bitunsigned number.
Range: {NCON*2 : (224-1)}
The FS450 synthesizes a 27-85 MHz clock from the 27 MHz TV_CKIN and supplies this clock
(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous tothe RGB data and Sync information. This clock has a 1.5 Hz resolution and can be adjusted so the VGAscaled input data rate exactly matches the CCIR 656 data output rate.
Frequency VGA / Frequency 656 = # VGA Pixels / # 656 Pixels x # VGA Lines / # 656 Lines
Frequency VGA / Frequency 656 = NCON / NCOD x M / N
Example: for SVGA mode, typ. total pixels x lines ~ 1024 x 625; let M=512, N=128:
NTSC: NCOD = 858 x 525 x 512 / 128 = 1,801,800PAL: NCOD = 8 x 625 x 512 / 128 = 2,160,000
JUNE, 2000, VERSION 1.227COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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6.2.10 APO, ALO, AFO - Auxiliary Pixel, Line, and Field OffsetsAuxiliary Pixel Offset Low (18)
7APO7
6APO6
5APO5
4APO4
3APO3
2APO2
1APO1
0APO0
Auxiliary Pixel Offset High (19)
70
60
50
40
30
20
1APO9
0APO8
Auxiliary Line Offset (1A)
7-6ALO6
5ALO5
4ALO4
3ALO3
2ALO2
1ALO1
0ALO0
Not Used (1B)
70
60
50
40
30
20
10
00
Auxiliary Field Offset (1C)
70
60
50
40
30
20
10
0AFO0
Not Used (1D)
70
60
50
40
30
20
10
00
Reg19, 18
Bit#9-0
Bit NameAPO9-0
Description
Auxiliary Pixel Offset [9:0]. Number of 27MHz cycles of
delay/advance of the Auxiliary Video Reference signals. APO is a10 bit signed number.
Auxiliary Line Offset [6:0]. Number of lines of delay/advance ofthe Auxiliary Video Reference signals. AFO is a 7 bit signednumber.
Auxiliary Field Offset [0]. Inverts the field of the Auxiliary VideoReference signals.
1A6-0ALO6-0
1C0AFO
APO Range: {-512 : 511}, ALO Range: {- : 63}, AFO Range: {0 : 1}
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6.2.11 HSOUTWID, HSOUTST, HSOUTEND - HSync Out Width, Starting andEnding Edge
HSync Out Width Low (1E)
7
HSOUTWID7
6
HSOUTWID6
5
HSOUTWID5
4
HSOUTWID4
3
HSOUTWID3
2
HSOUTWID2
1
HSOUTWID1
0
HSOUTWID0
HSync Out Width High (1F)
7
0
6
0
5
0
4
0
3
0
2
HSOUTWID10
1
HSOUTWID9
0
HSOUTWID8
HSync Out Starting Edge Low (20)
7
HSOUTST7
6
HSOUTST6
5
HSOUTST5
4
HSOUTST4
3
HSOUTST3
2
HSOUTST2
1
HSOUTST1
0
HSOUTST0
HSync Out Starting Edge High (21)
7
0
6
0
5
0
4
0
3
0
2
HSOUTST10
1
HSOUTST9
0
HSOUTST8
HSync Out Ending Edge Low (22)
7
HSOUTEND7
6
HSOUTEND6
5
HSOUTEND5
4
HSOUTEND4
3
HSOUTEND3
2
HSOUTEND2
1
HSOUTEND1
0
HSOUTEND0
HSync Out Ending Edge High (23)
7
0
6
0
5
0
4
0
3
0
2
HSOUTEND10
1
HSOUTEND9
0
HSOUTEND8
Reg1F, 1E21, 2023, 22
Bit#10-010-010-0
Bit NameHSOUTWID10-0HSOUTST10-0HSOUTEND10-0
Description
HSync Out Width [10:0]. Width of HSync Out during a frame.HSync Starting Edge [10:0]. Starting edge of HSync Out during aframe.
HSync Ending Edge [10:0]. Ending edge of HSync Out during aframe.
Range of HSOUTWID, HSOUTST, and HSOUTEND: {0 : 2048}
JUNE, 2000, VERSION 1.229COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
元器件交易网www.cecb2b.com
FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
TV_HSTARTStart and EndComparatorTV_HENDTV_VSTARTTV_VENDTV_FIELD
TV PixelCounterHysteresisComparatorFLT_HSTARTFLT_VSTARTFLT_FIELD
LoadAux PixelCounterTV LineCounterTV FieldCounterAux LineCounterAux FieldCounterSyncComparatorAUX_HREF
AUX_VREF
Figure 8: CCIR 656 Timing Block Diagram
The TV and Auxiliary Pixel/Line/Field Counters are freewheeling counters that are only loaded/reloadedduring an error condition. If the value of the TV Pixel/Line/Field Counters are within 4 TV pixels of the idealvalues during a Frame Start, no adjustment to the freewheeling counters are made. However, if the valuesexceeds 4 pixels (150 nsec) the ideal values, the TV Pixel/Line/Field Counters are reloaded and the TVCounter Acquisition Flag is set.
When the TV Pixel/Line/Field Counters are reloaded, the Auxiliary Pixel/Line/Field Counters are alsoreloaded. However, their load values are offset from the TV counter by the Auxiliary Pixel, Line, and FieldOffset values stored in its I2C registers (APO, ALO, and AFO). From these counters the Auxiliary
Horizontal and Vertical Syncs are formed. This feature allows a user to program advance timing signals tocompensate for external hardware processing latency when doing a mix/overlay with FS450’s CCIR 656input and output.
The FIFO Latency register delays the Frame Start occurrence by 4x its value in 27MHz clock cycles. Thisdelays the output 656 timing with respect to the input VGA timing and allows the FS450’s FIFO to fillappropriately before a FIFO read is initiated.
JUNE, 2000, VERSION 1.230COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
元器件交易网www.cecb2b.com
FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
1716
HREF
2761440
12345678
VREF
PIXEL NO. 1
PIXEL NO. 1006
2632265266267268269270
VREF
PIXEL NO. 1
PIXEL NO. 1
Figure 9: Auxiliary NTSC Reference Signals
1728
HREF
2881440
12345678
VREF
PIXEL NO. 1
PIXEL NO. 1006
313314315316317318319320
VREF
PIXEL NO. 1
PIXEL NO. 134
Figure 10: Auxiliary PAL Reference Signals
JUNE, 2000, VERSION 1.231COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
元器件交易网www.cecb2b.com
FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.12 SHP, FLK - Sharpness and Flicker FilterSharpness Low (24)
70
60
50
4SHP4
3SHP3
2SHP2
1SHP1
0SHP0
Sharpness High (25)
70
60
50
40
30
20
10
00
Reg24
Bit#4-0
Bit NameSHP4-0
Description
Flicker Filter Sharpness [4-0]. SHP accentuates the joint highvertical - high horizontal frequencies to sharpen edges. SHP is anunsigned number.
Range: {0 : 31} Provides 0 to 31/16 (6 dB) joint high horizontal and vertical frequency boost.
Flicker Filter Coefficient Low (26)
70
60
50
4FLK4
3FLK3
2FLK2
1FLK1
0FLK0
Flicker Filter Coefficient Low (27)
70
60
50
40
30
20
10
00
Reg26
Bit#4-0
Bit NameFLK4-0
Description
Flicker Filter Coefficient [4:0]. Provides weighting factor for 3line flicker filter. FLK is an unsigned number.
Range: {0 : 23}
Notes:
The FS450 Flicker Filter is more complex than a Three Line Average (TLA) flicker filter. The FS450 flicker filterincludes a variable vertical filter response in addition to a sharpness function. Adjusting the FLK Coefficientmodifies the vertical filter from no filtering (FLK = 0) to a Three Line Average (FLK = 16), giving the user the bestchoice in filtering options.
In addition to the variable vertical settings, the FS450 flicker filter has a sharpness function. This function is a twodimensional peaking function which accentuates the joint high vertical - high horizontal spatial frequencies (an\"edge enhancer\"). The three line variable two dimensional flicker filter is formed by summing the unit impulsefunction with a vertical flicker function scaled by FLK (Flicker Coefficient) and the peaking function which is scaledby SHP (Sharpness Coefficient). The FLK and SHP variables have 5 bits of resolutions, with a usable a rangefrom 0 to 16/16 for FLK, and 0 to 31/16 for SHP.
JUNE, 2000, VERSION 1.232COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.13 REV - Revision NumberPart Number (32)
7REV7
6REV6
5REV5
4REV4
3REV3
2REV2
1REV1
0REV0
Revision Number (33)
7REV15
6REV14
5REV13
4REV12
3REV11
2REV10
1REV9
0REV8
Reg33,32
Bit#15-0
Bit NameREV15-0
Description
Revision Number [15:0]. Identifies the revision for software IDpurposes (Rev A = 0, Rev B = 1).
JUNE, 2000, VERSION 1.233COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.14 MISC - Miscellaneous Bits 34, 35 RegisterMiscellaneous Bits Register (34)
70
6
0
5NCO_LOAD1
4NCO_LOAD0
30
20
10
00
Miscellaneous Bits Register (35)
7GTLIO_PD
60
50
40
30
20
1VGACKDIV
00
Reg34
Bit#
5,4
Bit Name
NCO_LOAD1-0
Description
NCO Load Control Bits. The PLL M and N dividers and theNCO Numerator (NCON) and denominator (NCOD) share thesame address (separate memory). The NCO Load Control bitsdetermine which registers are loaded when the NCON and
NCOD registers are written (see table below). M uses the lower11 bits of NCON, and N uses the lower 11 bits of NCOD.VGA Clock Divide. Setting this bit divides the internal clock by2 when the VGA input is in decimation (for XGA) mode.GTL I/O Power Down. Setting this bit puts all the GTL pinsinto power down mode.
3535
17
VGACKDIVGTLIO_PD
Notes:
NCO_LOAD
012
3
Meaning
Load NCO Numerator and Denominator only.Load M and N PLL Dividers only.
Load NCO Numerator and Denominator and
set M=512, N=128.
Load M and N PLL Dividers and set NCO
Numerator and Denominator both to 50.Table 5: NCO_LOAD Control Bits
1) M is loaded with the desired value -22) N is loaded with the desired value -1
3) Using the 24 bit NCON and NCOD yields a very fine frequency resolution of 1.5 Hz but dithers the clock.
The speed of the clock dither is sufficiently limited by the narrowband (around 5 kHz) PLL to prevent anyproblem with data transfers to the FS450. In fact, it provides an advantage for passing EMI certificationand behaves much like off the shelf dithered clocks designed specifically for that purpose.
4) Using the 11 bit M/N ratio gives a frequency resolution of 13 kHz, but it has no dithering. This is ideal for
dual VGA monitor and TV applications. Dithering the clock to a VGA controller makes the lines wiggle onthe connected VGA monitor, making it difficult to read. This however limits the scaling possibilities, andclose attention has to be paid to the factors of the VGA/TV pixels and lines so that they cancel down to 11bit M and N numbers.
5) Both M/N and Numerator/Denominator can be used together, to generate a compromise performance.
JUNE, 2000, VERSION 1.234COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
元器件交易网www.cecb2b.com
FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.15 FIFOL, FIFOH - FIFO Status Port Full/EmptyFIFO Status Port Full (36)
7FFOL7
6FFOL6
5FFOL5
4FFOL4
3FFOL3
2FFOL2
1FFOL1
0FFOL0
FIFO Status Port Empty (37)
7FFOH7
6FFOH6
5FFOH5
4FFOH4
3FFOH3
2FFOH2
1FFOH1
0FFOH0
Reg36
Bit#7-0
Bit NameFFOL7-0
Description
FIFO Status Port Full [7:0]. Maximum number of FIFO memorylocations underrun during the VGA image (multiply by 4 to getnumber of pixels corrupted). Unsigned number.
FIFO Status Port Empty [7:0]. Maximum number of FIFO
memory locations used during a VGA frame (multiply by 4 to getnumber of pixels filled). Unsigned number.
377-0FFOH7-0
Range: {0 : 255}
6.2.16 FFO_LAT - FIFO LatencyFIFO Latency Low (38)
7FFO_LAT7
6FFO_LAT6
5FFO_LAT5
4FFO_LAT4
3FFO_LAT3
2FFO_LAT2
1FFO_LAT1
0FFO_LAT0
FIFO Latency High High (39)
70
60
50
40
30
20
10
00
Reg38
Bit#7-0
Bit Name
FFO_LAT7-0
Description
FIFO Latency [7:0]. Number of output clock cycles between theinitiation of VGA writes to the FIFO memory and the TV reads fromit. Multiply by 4 to get the number of 27 MHz clock delays.
Range: {0 : 255}
JUNE, 2000, VERSION 1.235COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.17 VSOUTWID, VSOUTST, VSOUTEND - VSync Out Width, Starting andEnding Edge
VSync Out Width Low (3A)
7
VSOUTWID7
6
VSOUTWID6
5
VSOUTWID5
4
VSOUTWID4
3
VSOUTWID3
2
VSOUTWID2
1
VSOUTWID1
0
VSOUTWID0
VSync Out Width High (3B)
7
0
6
0
5
0
4
0
3
0
2
VSOUTWID10
1
VSOUTWID9
0
VSOUTWID8
VSync Out Starting Edge Low (3C)
7
VSOUTST7
6
VSOUTST6
5
VSOUTST5
4
VSOUTST4
3
VSOUTST3
2
VSOUTST2
1
VSOUTST1
0
VSOUTST0
VSync Out Starting Edge High (3D)
7
0
6
0
5
0
4
0
3
0
2
VSOUTST10
1
VSOUTST9
0
VSOUTST8
VSync Out Ending Edge Low (3E)
7
VSOUTEND7
6
VSOUTEND6
5
VSOUTEND5
4
VSOUTEND4
3
VSOUTEND3
2
VSOUTEND2
1
VSOUTEND1
0
VSOUTEND0
VSync Out Ending Edge High (3F)
7
0
6
0
5
0
4
0
3
0
2
VSOUTEND10
1
VSOUTEND9
0
VSOUTEND8
Reg3B, 3A3D, 3C3F, 3E
Bit#10-010-010-0
Bit NameVSOUTWID10-0VSOUTST10-0VSOUTEND10-0
Description
VSync Out Width [10:0]. Width of VSync Out during a frame.VSync Starting Edge [10:0]. Starting edge of VSync Out during aframe.
VSync Ending Edge [10:0]. Ending edge of VSync Out during aframe.
Range of VSOUTWID, VSOUTST, and VSOUTEND: {0 : 2048}
JUNE, 2000, VERSION 1.236COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.18 CHR_FREQ - Chroma Subcarrier FrequencyCHR_FREQ (40)
7
CHR_FREQ31
6
CHR_FREQ30
5
CHR_FREQ29
4
CHR_FREQ28
3
CHR_FREQ27
2
CHR_FREQ26
1
CHR_FREQ25
0
CHR_FREQ24
CHR_FREQ (41)
7
CHR_FREQ15
6
CHR_FREQ14
5
CHR_FREQ13
4
CHR_FREQ12
3
CHR_FREQ11
2
CHR_FREQ10
1
CHR_FREQ9
0
CHR_FREQ8
CHR_FREQ (42)
7
CHR_FREQ15
6
CHR_FREQ14
5
CHR_FREQ13
4
CHR_FREQ12
3
CHR_FREQ11
2
CHR_FREQ10
1
CHR_FREQ9
0
CHR_FREQ8
CHR_FREQ (43)
7
CHR_FREQ7
6
CHR_FREQ6
5
CHR_FREQ5
4
CHR_FREQ4
3
CHR_FREQ3
2
CHR_FREQ2
1
CHR_FREQ1
0
CHR_FREQ0
Reg
40,41,42,43
Bit#all
Bit Name
CHR_FREQ31-0
Description
Chroma Subcarrier Frequency. Sets the subcarrierfrequency, = subcarrier/27,000,000*2^32..
JUNE, 2000, VERSION 1.237COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.19 Chroma Phase, Miscellaneous Bits 45Chroma Phase (44)
7
CHR_PHASE7
6
CHR_PHASE6
5
CHR_PHASE5
4
CHR_PHASE4
3
CHR_PHASE3
2
CHR_PHASE2
1
CHR_PHASE1
0
CHR_PHASE0
Miscellaneous Bit Register 45 (45)
70
60
50
40
30
20
1CLRBAR
0BYPYCLP
Reg4445
Bit#7-00
Bit Name
CHR_PHASE7-0
Description
Pre-set Subcarrier Phase [7:0]. Value for pre-set subcarrierphase (only upper 8 bit programmable, lower 24 bits =0).Bypass Y Clamp. Allows for non-standard range of Luma on Y-inputs. 0=Luma expected range [16:235], and clamped to thisrange. 1=Luma expected in range [0:255] and no clamping isperformed.
Color Bar Mode. Causes the YC inputs in the encoder to be
ignored and forces a color bar pattern onto the input. The color barpattern is a repeating sequence of 8 colors at 75% amplitude and100% saturation.
BYPYCLP
451CLRBAR
JUNE, 2000, VERSION 1.238COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.20 Miscellaneous Bits Registers 46 and 47Miscellaneous Bits Register 46
7
RGB_SETUP
6
RGB_SYNC2
5
RGB_SYNC1
4
RGB_SYNC0
3
YC_DELAY2
2
YC_DELAY1
1
YC_DELAY0
0
CVBS_EN
Miscellaneous Bits Register 47
7
0
6
0
5
0
4
0
3
CHR_BW1
2
COMP_YUV
1
COMP_GAIN1
0
COMP_GAIN0
Reg46
Bit#03-1
Bit Name
CVBS_ENYC_DELAY2-0
Description
CVBS Enable. Enables composite and luma outputs.
YC Delay. Relative pipeline delay between luma and chromaoutputs (4=0 clock; 0=luma lags chroma by 4 clocks; 7=chromalags luma by 3 clocks).
RGB Sync. Provide sync to RGB components: [2]=1, sync onred; [1]=1, sync on green; [0]=1, sync on blue.
RGB Setup. Provide black level (0) or blank level (1) setup forRGB outputs..
Composite Chroma Gain. Percentage of chroma used incomposite output: 00=100%, 01=25%, 10=50%, 11=75%.Component YUV. Enables bypass on the RGB inputs sendingcomponent data YUV through.
Chroma Filter Bandwidth Control. 00=narrow, 01=wide,
10=extra wide, 11=ultra wide (see Miscellaneous Bit Register 74for bit 0).
474747
6-471-023
RGB_SYNC2-0
RGB_SETUP
COMP_GAIN1-0
COMP_YUV
CHR_BW1
JUNE, 2000, VERSION 1.239COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.21 HSync Width (48), Burst Width (49)HSync Width (48)
7
HSYNC_WID7
6
HSYNC_WID6
5
HSYNC_WID5
4
HSYNC_WID4
3
HSYNC_WID3
2
HSYNC_WID2
1
HSYNC_WID1
0
HSYNC_WID0
Burst Width (49)
7
-
6
BURST_WID6
5
BURST_WID5
4
BURST_WID4
3
BURST_WID3
2
BURST_WID2
1
BURST_WID1
0
BURST_WID0
Reg4849
Bit#7-06-0
Bit Name
HSYNC_WID7-0
Description
HSync Width. Width of HSync in 27MHz clocks (LSB bit 0 istied to zero).
Burst Width. Width of the burst in 27MHz clocks.
BURST_WID6-0
6.2.22 Back Porch Width (4A), Cb Burst Amplitude (4B)Back Porch Width (4A)
7BPORCH7
6BPORCH6
5BPORCH5
4BPORCH4
3BPORCH3
2BPORCH2
1BPORCH1
0BPORCH0
Cb Burst Amplitude (4B)
7
6
5
4
3
2
1
0
CB_BURST7CB_BURST6CB_BURST5CB_BURST4CB_BURST3CB_BURST2CB_BURST1CB_BURST0
Reg4A4B
Bit#7-07-0
Bit NameBPORCH7-0
CB_BURST7-0
Description
Back Porch Width. Width of the back porch in 27MHz clocks(LSB bit 0 is tied to zero).
Cb Burst Amplitude Setting. Range {-127:127}
JUNE, 2000, VERSION 1.240COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.23 Cr Burst Amplitude (4C), Miscellaneous Bits Register 4DCr Burst Amplitude (4C)
7
CR_BURST7
6
CR_BURST6
5
CR_BURST5
4
CR_BURST4
3
CR_BURST3
2
CR_BURST2
1
CR_BURST1
0
CR_BURST0
Miscellaneous Bits Register 4D
70
60
50
40
30
20
1SLV_THRS
0SLV_MOD
Reg4C4D
Bit#7-00
Bit Name
CR_BURST7-0
Description
Cr Burst Amplitude Setting. Range {-127:127}
Slave Mode. Enable bit for Full Slave Mode timing. This doesnot enable Partial Save Mode and should be cleared unless FullSlave Mode operation is required.
Slave Mode Threshold. Controls the threshold at which theencoder begins the horizontal line adjustments (0=0 line, 1=30line).
SLV_MOD
4D1SLV_THRS
6.2.24 Black Level (4E)Black Level (4E)
7
BLACK_LVL9
6
BLACK_LVL8
5
BLACK_LVL7
4
BLACK_LVL6
3
BLACK_LVL5
2
BLACK_LVL4
1
BLACK_LVL3
0
BLACK_LVL2
Black Level (4F)
7
0
6
0
5
0
4
0
3
0
2
0
1
BLACK_LVL1
0
BLACK_LVL0
Reg4E, 4F
Bit#7-0, 1-0
Bit Name
BLACK_LVL9-0
Description
Black Level. Used to create a setup.
JUNE, 2000, VERSION 1.241COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.25 Blank Level (50)Blank Level (50)
7
BLANK_LVL9
6
BLANK_LVL8
5
BLANK_LVL7
4
BLANK_LVL6
3
BLANK_LVL5
2
BLANK_LVL4
1
BLANK_LVL3
0
BLANK_LVL2
Blank Level (51)
7
0
6
0
5
0
4
0
3
0
2
0
1
BLANK_LVL1
0
BLANK_LVL0
Reg50, 51
Bit#7-0, 1-0
Bit Name
BLANK_LVL9-0
Description
Blanking Level. Blanking level during non VBI.
6.2.26 Number of Lines (57-58)Unused (56)
Number of Lines (57)
7
NUM_LINES9
6
NUM_LINES 8
5
NUM_LINES7
4
NUM_LINES6
3
NUM_LINES5
2
NUM_LINES4
1
NUM_LINES3
0
NUM_LINES2
Number of Lines (58)
7
0
6
0
5
0
4
0
3
0
2
0
1
NUM_LINES1
0
NUM_LINES 0
Unused (59)
Reg57, 58
Bit#7-0, 1-0
Bit Name
NUM_LINES9-0
Description
Number of Lines. Number of lines in a frame. Note that an oddnumber implies an interlaced image and an even number impliesa progressive image.
JUNE, 2000, VERSION 1.242COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.27 White Level (5E)White Level (5E)
7
WHITE_LVL9
6
WHITE_LVL8
5
WHITE_LVL7
4
WHITE_LVL6
3
WHITE_LVL5
2
WHITE_LVL4
1
WHITE_LVL3
0
WHITE_LVL2
White Level (5F)
7
0
6
0
5
0
4
0
3
0
2
0
1
WHITE_LVL1
0
WHITE_LVL0
Reg5E, 5F
Bit#7-0, 1-0
Bit Name
WHITE_LVL9-0
DescriptionWhite Level.
6.2.28 Cb Color Saturation (60)Cb Color Saturation (60)
7CB_GAIN7
6CB_GAIN6
5CB_GAIN5
4CB_GAIN4
3CB_GAIN3
2CB_GAIN2
1CB_GAIN1
0CB_GAIN0
Unused (61)
Reg60
Bit#7-0
Bit NameCB_GAIN7-0
Description
Cb Color Saturation Control. (1 LSB = 1/128).
6.2.29 Cr Color Saturation (62)Cb Color Saturation (60)
7CR_GAIN7
6CR_GAIN6
5CR_GAIN5
4CR_GAIN4
3CR_GAIN3
2CR_GAIN2
1CR_GAIN1
0CR_GAIN0
Unused (63)
Reg62
Bit#7-0
Bit NameCR_GAIN7-0
Description
Cr Color Saturation Control. (1 LSB = 1/128).
JUNE, 2000, VERSION 1.243COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.30 Tint (65)Unused ()Tint (65)
7TINT7
6TINT6
5TINT5
4TINT4
3TINT3
2TINT2
1TINT1
0TINT0
Reg65
Bit#7-0
Bit NameTINT7-0
Description
Tint Adjustment on Chroma.
6.2.31 Width of Breezeway (69)Unused (68)
Width of Breezeway (69)
70
60
50
4BR_WAY4
3BR_WAY3
2BR_WAY2
1BR_WAY1
0BR_WAY0
Reg69
Bit#4-0
Bit NameBR_WAY4-0
Description
Width of Breezeway. In 27MHz clocks.
6.2.32 Front Porch (6C)Front Porch (6C)
7
0
6
0
5
FR_PORCH5
4
FR_PORCH4
3
FR_PORCH3
2
FR_PORCH2
1
FR_PORCH1
0
FR_PORCH0
Unused (6D)
Reg6C
Bit#5-0
Bit Name
FR_PORCH5-0
Description
Front Porch. Width of front porch in 27MHz clocks (LSB bit 0tied to zero).
JUNE, 2000, VERSION 1.244COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.33 Active Video Line (71-72), First Video Line (73)Unused (70)
Active Video Line (71)
7
ACT_LINE10
6ACT_LINE9
5ACT_LINE8
4ACT_LINE7
3ACT_LINE6
2ACT_LINE5
1ACT_LINE4
0ACT_LINE3
Active Video Line (72)
70
60
50
40
30
2ACT_LINE2
1ACT_LINE1
0ACT_LINE0
First Video Line (73)
71ST_LINE7
61ST_LINE6
51ST_LINE5
41ST_LINE4
31ST_LINE3
21ST_LINE2
11ST_LINE1
01ST_LINE0
Reg71, 72
Bit#7-0, 2-0
Bit Name
ACT_LINE10-0
Description
Active Video Line. Number of 27MHz clocks in active video line(1440 setting refers to 720 of luma pixels and 720 chroma (Cband Cr) pixels; the LSB bits [1:0] are tied to zero).
First Line of Video. Line number for the first line of video in afield.
737-01ST_LINE7-0
JUNE, 2000, VERSION 1.245COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.34 Miscellaneous Bits 74, Sync Level (75)Miscellaneous Bit Register 74
7
UV_ORDER
6
PAL_MODE
5CHR_BW0
4
INVERT_TOP
3
SYS625_50
2CPHASE1
1CPHASE0
0VSYNC5
Sync Level (75)
7
SYNC_LVL7
6
SYNC_LVL6
5
SYNC_LVL5
4
SYNC_LVL4
3
SYNC_LVL3
2
SYNC_LVL2
1
SYNC_LVL1
0
SYNC_LVL0
Reg7474
Bit#02-1
Bit NameVSYNC5CPHASE1-0
Description
VSync Equalization Pulses. 0=6 and 1=5 VSync equalizationand broad pulses.
Resetting Period of Carrier Clock. 0=every 8 fields, 1=every 4fields, 2=every other line, 3=once before any chroma burst and thennever reset again.
System Field Format. 0=525 lines and 59.94 fields/sec system;1=625 lines and 50 fields/sec system..
Invert Field ID Polarity. Inverts the polarity of the encoder's fieldidentification signal.
Chroma Filter Bandwidth Control. 00=narrow, 01=wide,
10=extra wide, 11=ultra wide (see Miscellaneous Bit Register 47for bit 1).
PAL or NTSC Mode. 0=NTSC, 1=PAL.
UV Order. Switches ordering of Cb and Cr inputs.Sync Level. Sync level during non-VBI lines.
747474
345
SYS625_50
INVERT_TOP
CHR_BW0
747475
677-0
PAL_MODEUV_ORDER
SYNC_LVL7-0
JUNE, 2000, VERSION 1.246COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.35 VBI Blank Level (7C)VBI Blank Level (7C)
7
VBIBL_LVL9
6
VBIBL_LVL8
5
VBIBL_LVL7
4
VBIBL_LVL6
3
VBIBL_LVL5
2
VBIBL_LVL4
1
VBIBL_LVL3
0
VBIBL_LVL2
VBI Blank Level (7D)
7
0
6
0
5
0
4
0
3
0
2
0
1
VBIBL_LVL1
0
VBIBL_LVL0
Reg7C, 7D
Bit#7-0, 1-0
Bit Name
VBIBL_LVL9-0
Description
VBI Blanking Level. Blanking level during VBI lines.
6.2.36 SOFT_RST, ENC_VER - Encoder Soft Reset, Encoder VersionEncoder Soft Reset (7E)
70
60
50
40
30
20
10
0
SOFT_RST
Encoder Version Number (7F)
7ENC_VER7
6ENC_VER6
5ENC_VER5
4ENC_VER4
3ENC_VER3
2ENC_VER2
1ENC_VER1
0ENC_VER0
Reg7E7F
Bit#07-0
Bit Name
SOFT_RSTENC_VER7-0
Description
Encoder Soft Reset. Writing to this bit resets the video encoder.Encoder Version Number. Contains the version of the encoder.This is a read-only register.
JUNE, 2000, VERSION 1.247COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.37 Misc. Bit Reg. 80, WSS Clock (81-82), WSS Data F1(83-85)Miscellaneous Bit Register 80
70
6
WSS_F1EN
5
WSSF0_EN
4
WSS_TYPE
3
WSS_CLKBY
2
WSS_EDGE1
1
WSS_EDGE0
00
WSS Clock (81)
7
WSS_CLK11
6
WSS_CLK10
5
WSS_CLK9
4
WSS_CLK8
3
WSS_CLK7
2
WSS_CLK6
1
WSS_CLK5
0
WSS_CLK4
WSS Clock (82)
7
0
6
0
5
0
4
0
3
WSS_CLK3
2
WSS_CLK2
1
WSS_CLK1
0
WSS_CLK0
WSS Data Field 1 (83)
7
WSS_DATF019
6
WSS_DATF018
5
WSS_DATF017
4
WSS_DATF016
3
WSS_DATF015
2
WSS_DATF014
1
WSS_DATF013
0
WSS_DATF012
WSS Data Field 1 (84)
7
WSS_DATF011
6
WSS_DATF010
5
WSS_DATF09
4
WSS_DATF08
3
WSS_DATF07
2
WSS_DATF06
1
WSS_DATF05
0
WSS_DATF04
WSS Data Field 1 (85)
70Reg
80
60Bit#2-1
50Bit Name
WSS_EDGE1-0
40
3
WSS_DATF03
2
WSS_DATF02
1
WSS_DATF01
0
WSS_DATF00
Description
WSS Edge Rate Control. Edge rates are proportional to thefrequency of the WSS clock, but can also be scaled by theWSS_EDGE parameter. Higher numbers indicate faster riseand fall times on the WSS pulses.
WSS Clock Bypass. Typically this is set=1 in NTSC and 0 inPAL. =1 Causes the chroma clock to be used as the WSSclock, =0 forces the local 12-bit WSS clock to be used.WSS Type. 1=PAL, ITU-R BT.1119-2, 0=NTSC, EIAJ CPR-1204
WSS Field 0 Enable. Enables WSS signal in Field 0.WSS Field 1 Enable. Enables WSS signal in Field 1.WSS Clock Frequency. Calculated from:
WSS Clock Frequency / Encoder Clock Frequency.WSS Data for Field 1. A waveform only appears whenWSSF1_EN=1.
48
COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
803WSS_CLKBY
80808081, 8283,84,85
4567-0, 3-07-0,7-0,3-0
WSS_TYPE
WSSF0_ENWSSF1_ENWSS_CLK11-0WSS_DATAF119-0
JUNE, 2000, VERSION 1.2
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.38 WSS Data Field 0(86-88), WSS Line Number Field 1 ()WSS Data Field 0 (86)
7
WSS_DATF019
6
WSS_DATF018
5
WSS_DATF017
4
WSS_DATF016
3
WSS_DATF015
2
WSS_DATF014
1
WSS_DATF013
0
WSS_DATF012
WSS Data Field 0 (87)
7
WSS_DATF011
6
WSS_DATF010
5
WSS_DATF09
4
WSS_DATF08
3
WSS_DATF07
2
WSS_DATF06
1
WSS_DATF05
0
WSS_DATF04
WSS Data Field 0 (88)
70
60
50
40
3
WSS_DATF03
2
WSS_DATF02
1
WSS_DATF01
0
WSS_DATF00
WSS Line Number Field 1 ()
7
6
5
4
3
2
1
0
WSS_LNF17WSS_LNF16WSS_LNF15WSS_LNF14WSS_LNF13WSS_LNF12WSS_LNF11WSS_LNF10
Reg
86,87,88
Bit#7-0,7-0,3-07-0
Bit Name
WSS_DATAF019-0WSS_LINEF17-0
Description
WSS Data for Field 0. A waveform only appears whenWSSF0_EN=1.
Field 1 WSS Line. Line number (relative to the previousVSync) at which the WSS data will appear in Field 1.
JUNE, 2000, VERSION 1.249COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
6.2.39 WSS Field 0 Line Number, WSS Level, Misc. Bits Reg. 8D (8A-8D)WSS Field 0 Line Number (8A)
7
6
5
4
3
2
1
0
WSS_LNF07WSS_LNF06WSS_LNF05WSS_LNF04WSS_LNF03WSS_LNF02WSS_LNF01WSS_LNF00
WSS Level (8B)
7WSS_LVL9
6WSS_LVL8
5WSS_LVL7
4WSS_LVL6
3WSS_LVL5
2WSS_LVL4
1WSS_LVL3
0WSS_LVL2
WSS Level (8C)
70
60
50
40
30
20
1WSS_LVL1
0WSS_LVL0
Miscellaneous Bits Register 8D
7
0
6
0
5
0
4
NOTCH_EN
3
NOTCH_WD
2
NOTCH_FRQ2
1
NOTCH_FRQ1
0
NOTCH_FRQ0
Reg8A8B, 8A8D8D8D
Bit#7-07-0, 1-02-034
NOTCH_FRQ
Bit NameWSS_LNF07-0WSS_LVL9-0
Description
Field 0 WSS Line. Line number (relative to the previousVSync) at which the WSS data will appear in Field 0.
WSS High Level. WSS waveform will rise from VBIBL_LVL toWSS_LVL in a 0 to 1 transition.
which the notch will be centered (see table below).
NOTCH_FRQ2-0Notch Frequency. Selects from 8 possible frequencies around
NOTCH_WDNOTCH_EN
Description
Notch Filter Wide Bandwidth. 1=wide, 0=narrow.Notch Filter Enable. 1=On, 0=Off.
Notch Y Value1 + 1/8 + 1/161 + 1/8 + 1/
1 + 1/8 + 1/16 (wide)1 (narrow)1 - 1/128
1 - 1/32 - 1/
1 - 1/8 - 1/32 -1/128 (wide)1 - 1/4 + 1/32 -1/128 (narrow)1 - 1/8 - 1/16 - 1/321 - 1/4 - 1/32
Notch Y Value
1.18751.14061.09381.00000.99220.95310.83590.77340.78130.7188
01234567
CCIR 601 NTSCSQ Pixel NTSCSQ Pixel PALCCIR 601 PAL
Table 6: NOTCH_FRQ Values
JUNE, 2000, VERSION 1.2
50
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Hex
IndxRegister
40447460624C4B74747448494A6C6971507C4E5E7557
CHR_FREQCHR_PHASECPHASECR_GAINCB_GAINCR_BURSTCB_BURSTSYS625_50VSYNC5PAL_MODEHSYNC_WIDBURST_WIDBPORCH
FRNT_PORCHBREEZE_WAYACTIVELINEBLANK_LVLWSS_LVLBLACK_LVLWHITE_LVLSYNC_LVLLINE_FRAME
Combinatio
NTSC
0x21f07c1f
PAL
0x2a098acb
PAL-M
0x21e6efe3
PAL-N
0x2a098acb
n
PAL-N
0x21f69446
0213713705900012668118322214402402402828001652500145145314411112613824261440251251251800166250013713729410011266811832181440240240282800165250013713729411011261382426144024024028280016625001451453144111126681382426144025125125180016625
Table 7: Typical Register Values for Various Standards
JUNE, 2000, VERSION 1.251COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
7. Design and Layout Considerations
Careful circuit design and layout are key factors that insure a successful implementation of the FS450 in aproduct. The following guidelines will help insure that your design yields the best possible results.
7.1 Pixel Phase Lock Loop
• •
The analog supply for the Pixel PLL should always be clean and noise free to insure minimum jitter inthe PLL. Do not power other circuitry from the PLL supply.
The supply line VDDPA should be decoupled with a series resistor of 150W and a 4.7µF tantalum
capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100µF. Always have a 1000pF to 0.1µFcapacitor to remove high frequency noise.Use a solid ground plane under the FS450.
•
7.2 Video Output Filters
•
To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75Wtermination resistors and the first capacitor of the output filter close to the video output pins of theFS450.
7.3 Analog Power Supply Bypassing, Filtering, and Isolation
•
When possible, it is recommended that the analog supply voltages be fed from a linear voltage regulator.Switching power supply noise, and noise from the digital plane can induce visible artifacts into thedisplayed video. Always provide sufficient filtering and high frequency bypassing to insure that powersupply noise is minimized for visual as well as EMI reasons.
It is recommended that each power supply section be isolated with a ferrite bead and a 4.7µF capacitor.Where the power pins are so close together that the 0.1µF bypass capacitors are adjacent, considerchanging one of the adjacent capacitors to 100 to 1000pF to reduce higher frequency noise on thepower supply.
•
7.4 Power and Ground
•
Within the FS450, separate power is routed to functional sections: phase locked loop, D/A converters,digital processors and digital drivers. All ground pins should be connected to a common ground plane.Power pins should be segregated into analog and digital sections.
Clean analog power should be applied to the VDDPA, VDDOSC, and VDDDA pins. A 0.1 µF capacitor shouldbe placed adjacent to each group of pins. The capacitor connected to CBYPASS is critical, and it must beconnected to VDDDA to minimize noise at the D/A converter outputs. Chip capacitors are recommended.Digital power may be derived from system digital +3.3 volts. If necessary insert a ferrite bead in serieswith the supply trace. A 47 µF capacitor should be placed across the common +3.3 VDC for VDD andVDDDA to act as a reservoir for heavy currents drawn by D/A converters and internal memories. At leastone 0.1 µF capacitor should be located adjacent to VDD pins along each side of the FS450 to supplytransient currents.
•
•
JUNE, 2000, VERSION 1.252COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
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7.5 Interfacing to the FS450 in a Mixed Voltage Environment
As many devices designed today, the FS450 is powered by +3.3 Volts. However, 5 Volt devices are stillvery common today and will continue to be used for some time in the future. To meet this interfacerequirement the FS450 has 5 Volt tolerant inputs.
7.5.1 Interfacing to the SIO bus.
The SIO bus was developed previous to 3.3V logic processes. The SIO bus input voltage specification is 1.5Volts for VIL and 3.0 Volts for VIH. The FS450 is built on a 3.3 Volt process and has 5 Volt tolerant inputswith a VIL of 0.8 Volts and a VIH of 2.0 Volts.
For most applications this voltage difference is not an issue as the output drive low specification (VOL) of theSIO bus and the FS450 are both 0.4 Volts. However, in heavily loaded SIO busses the output VOL is notalways preserved.
An easy way to regain the 0.7 Volt difference in the VIL specification of the FS450 and the SIO bus is to biasthe FS450’s input negative by a diode drop (D1). The diode can be biased by a long-tail resistor pair or acurrent source pair. Shown below is the long-tail pair:
+12VR122KToI2C
D1ToFS450
R227K-12VFigure 11. SIO Translation Using Long-tail Resistors
D1 = 1N4148
The long-tail pair is a simple circuit but has the disadvantage of requiring higher voltage power supplies.Also, these supplies may have to powered up in a specific sequence so the surround circuits are not over-voltage.
The translation circuit below requires only one 5 Volt power supply and has no special sequence
requirements. In addition, the circuit offers a high impedance load (Q1 become reverse biased) to the SIObus when its power supply is removed. Unfortunately, it requires more parts. In applications wheretransistors are more readily available, R2 and R3 can be replaced with diode connected transistors.
JUNE, 2000, VERSION 1.253COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
+5V
R12.9KQ1ToI2C
R21.3KD1R31.2KQ2ToFS450
Figure 12. SIO Translation Using Current Mirrors
D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904
For applications with more than one supply, combinations of the above two circuits can be used. However,the simplest approach to this problem is to limit the loading on the SIO bus when possible. When this isnot possible, some of the SIO passive loads can be replaced with active ones. This will increase the SIOaccess speed without increasing the SIO output low drive current.
JUNE, 2000, VERSION 1.2COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
8. Specifications
8.1 Absolute Maximum and Recommended Ratings
(beyond which the device may be damaged)1 Parameter
Power Supply VoltagesVDD (Measured to VSS)
VDDAD (Measured to VSSAD)
VDDPA and VDDPF (Measured to VSSPA and VSSPF)VDDDA (Measured to VSSDA)
VSSAD, VSSPA, VSS, VSSPA, VSSDA (delta)Digital Inputs
3.3 V logic applied voltage (Measured to VSS)2Forced current 3, 4Analog Inputs
Applied Voltage (Measured to VSSAD)2Forced current 3, 4Digital Outputs
3.3 V logic applied voltage (Measured to VSS)2Forced current 3, 4Short circuit duration (single output in HIGH state toground)
Temperature
Operating, Ambient (RL=37.5Ω)Operating, Ambient (RL=75Ω)Junction
Thermal Resistance Junction to Ambient (typical), ØJAThermal Resistance Junction to Case (typical), ØJCLead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)1Storage1Electrostatic
Electrostatic Discharge5Notes:
1.Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed
only if Operating Conditions are not exceeded.
2.Applied voltage must be current limited to specified range.3.Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.5. EIAJ test method.
Min-0.3-0.3-0.3-0.3-0.3-0.3-10.0-0.3-10.0-0.3-6.0
Rec.3.0-3.63.0-3.63.0-3.63.0-3.6
Max3.83.83.83.80.3VDD + 0.310.0VDDDA + 0.3
10.0VDD + 0.36.01
UnitVVVVVVmAVmAVmAsecond
0-VDD0-VDD
0-VDD
00
-40
6570125565300220125±150
°C°C°C°C/W°C/W°C°C°CV
JUNE, 2000, VERSION 1.255COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
8.2 Electrical Characteristics
Parameter
Power Supply CurrentsIDD33.3 volt Digital current
IDDDA3.3 volt Analog currentIDDDA3.3 volt Analog DAC currentIDDOSC3.3 volt Crystal Oscillator currentIDDDPA3.3 volt VGA PLL currentIDDT3.3 volt Total CurrentLVTTL Inputs and OutputsCIInput CapacitanceCOOutput CapacitanceIIHInput Current, HIGHIILIILP
Input Current, LOW
Input Current, LOW with pull-up
ConditionsVGA Core
Clock=50MHzRL=37.5ΩRL=75Ω
Min
Typ1658515527055
VDD3 = 3.3 ± 0.3V,VIN = max.
VDD3 = 3.3 ± 0.3V,VIN = 0 V
VDD3 = 3.3 ± 0.3V,VIN = 0 V
105Max
UnitmAmAmA
mA
1010±10±10
pFpFµAµAµAVVmAmAVVpFpFµAµAVVVµAmAVVVKΩpF
-602.0
-10
VIHInput Voltage, Logic HIGHVILInput Voltage, Logic LOWIOHOutput Current, Logic HIGHIOLOutput Current, Logic LOWVOHOutput Voltage, HIGHVOLOutput Voltage, LOWGTL Inputs and OutputsCIInput CapacitanceCOOutput CapacitanceIIHInput Current, HIGHIILVIHVILVREFIOHIOLVOLAnalogVIREFVOCROUTCOUT
Input Current, LOW
Input Voltage, Logic HIGHInput Voltage, Logic LOWVoltage Reference RangeOutput Current, Logic HIGH1Output Current, Logic LOW1Output Voltage, LOW
DAC Current Reference VoltageVideo Output ComplianceVideo Output ResistanceVideo Output Capacitance
0.8-4.04.0
IOH = -4mAIOL = 4mA
2.4
0.4
44
VDD3 = 3.3 ± 0.3V,VIN = max.
VDD3 = 3.3 ± 0.3V,VIN = 0 V
VREF+.2TBD
0.9
VREF-.2TBD-1045.00.341.40288±10±10
IOL = 45mA
0.121.15-0.4
0.201.2761520
COUT = 0 mA,Freq. = 1 MHz
JUNE, 2000, VERSION 1.256COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
8.3 Switching Characteristics
ParameterClocksfCKINTV Encoder Reference Clock FrequencyfXTOLTV Reference Clock Frequency TolerancetPWHTTV Reference Clock Pulse Width, HIGHtPWLTTV Reference Clock Pulse Width, LOWfPCKINVGA Clock Positive Edge FrequencyfNCKINVGA Clock Negative Edge FrequencyfCOREVGA Core Frequency4fVCKOVGA Clock Output
tJIT-VCKVGA Clock Output Jitter (peak-to-peak)fPLLREFPLL Reference Clock FrequencyMPLL Numerator
tPWHVVGA Clock Positive Edge Pulse Width, HIGHtPWLVVGA Clock Negative Edge Pulse Width, LOWResetAssert fCKIN cycles on RESET\\ to reset the partDigital RGB Input PorttPDHVGA_PCKIN to Data Hold TimetNDHVGA_NCKIN to Data Hold TimetPSUVGA_PCKIN to Data Setup TimetNSUVGA_NCKIN to Data Setup TimeCCIR 656 Video Input and Output PorttTDHTV_CKIN to Data Hold TimetTSUTV_CKIN to Data Setup TimetTDOTV_CKIN to Data Out DelaySerial Microprocessor InterfacetDALSCL Pulse Width, LOWtDAHSCL Pulse Width, HIGHtSTAHSDA Start Hold Time
tSTASUSCL to SDA Setup Time (Stop)tSTOSUSCL to SDA Setup Time (Start)tBUFFSDA Stop Hold Time SetuptDSUSDA to SCL Data Setup TimetDHOSDA to SCL Data Hold Time
Conditions
Min
Typ227.0
30
15.015.027.027.027.0
over a cycle
245005.05.016001.51.5010.0
24.0
1.30.60.60.60.61.3300300
Max
UnitMHzppmnsnsMHzMHzMHzMHzpskHz
50
3
40/60 duty cycle40/60 duty cycle
85.085.050.085.02001001200
Clocksnsnsnsnsnsnsnsµsµsµsµsµsµsnsns
Notes:
1. GTL outputs are open drain, intended to drive 31 ohm termination from 1.8 volts.2. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C3. TV subcarrier acceptance band is ± 300 Hz.
4. VGA Core Frequency = VGA Clock Frequency/(UIM_DEC+1)
JUNE, 2000, VERSION 1.257COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
9. Mechanical Dimensions
9.1 100-Lead PQFP (KH) Package
SymbolAA1A2BCDD1EE1eLNNDNEαccc
InchesMin.
Max.
MillimetersMin.
Max.
3.00
0.05-2.552.750.250.400.100.2523.6024.2019.8020.2017.3018.2013.8014.20
0.65 BSC0.601.00
1003020
08°-
Notes
Notes:
1. All dimensions and tolerances
conform to ANSI Y14.5M-1982.
2. Controlling Dimension is millimeters3. Dimension “B” does not include
dambar protrusion. Allowabledambar protrusion shall be .08mm(.003in.) maximum in excess of the“B” dimension. Dambar cannot belocated on the lower radius or thefoot.
4. “L” is the length of terminal for
soldering to a substrate.5. “b” & “C” include lead finish
thickness.
3,55
4
1003020
Figure 13: Package Outline & Dimensions
JUNE, 2000, VERSION 1.258COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC.
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FS450, FS451PRELIMINARY PRODUCT DESCRIPTION
10. Revision History
October 13, 1999: First Release, V1.0.
March 7, 2000: Second Release, V1.1: Throughout: changed encoder registers (40-8D) from little endianto big endian; p. 1, new patent referenced; p.12, corrected table by adding VGA_CKOUTTL, specifying
proper clock for non-Intel designs, and proper Syncs for nVidia; p. 13, HSYNC_OUT & VSYNC_OUT are forSlave Mode; p. 14, CSYNC is active high and reverence output voltage is 1.276 V; p. 18 & 39, correctedwidth of Burst Width register; p. 29, added HSOUTWID, HSOUTST, HSOUTEND registers description; p.36, added VSOUTWID, VSOUTST, VSOUTEND registers description; p. 52, changes to 7.3 layoutconsiderations; p. 53-4, corrected 5V tolerant issues; p. 56, added VIREF.
June 24, 2000: Third Release, V1.2: minor updates for clarity & formatting, p. 52, updated analog bypassrecommendations; p. 58, added pin picture; p. 59, fixed part mark.
11. Order Information
Order Number444-2131444-2132Package Markings:
FOCUSEnhancementsiNet TV FS45x where x = 0, or 1; YY=year; WW=work week; R=Revision. Temperature Range 0°C to 65°C0°C to 65°C ScreeningCommercialCommercial Package100 Lead PQFP100 Lead PQFP Package Marking FS450ACFS451AC Please forward suggestions and corrections as soon as possible to the email address below. Theinformation herein is accurate to the best of FOCUS’ knowledge, but not all specifications havebeen characterized or tested at the time of the release of this document. Parameters will beupdated as soon as possible and updates made available. All parameters contained in this specification are guaranteed by design, characterization, sample testing or100% testing as appropriate. Focus Enhancements reserves the right to change products and specifications without notice. This information does not convey any license under patent rights of FocusEnhancements, Inc. or others. Critical Applications Policy Focus Enhancements components are not designed for use in Critical Applications. Critical Applicationsare products whose use may involve risks of death, personal injury, severe property damage or environmental damage or life support applications, devices, or systems, wherein a failure or malfunction ofthe component can reasonably be expected to result in death or personal injury. The user of FocusEnhancements components in Critical Applications assumes all risk of such use and indemnifies FocusEnhancements against all damages. FOCUS Enhancements, Inc. JUNE, 2000, VERSION 1.2 59 COPYRIGHT ©1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORMATION 元器件交易网www.cecb2b.com FS401, FS402, FS403PRODUCT SPECIFICATION REV. NO. 1.2 600 Research DriveWilmington, MA 01887www.FOCUSinfo.comPhone:Fax:Email:(978) 988-5888(978) 988-7555 info@FOCUSinfo.comJUNE, 2000, VERSION 1.260COPYRIGHT ©1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORMATION 因篇幅问题不能全部显示,请点此查看更多更全内容
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