GD_SPI_NAND_application_notes_Rev1.1

DPr Celoimnfinidearnytial 2. SPI NAND Flash Features:

• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4) • 06H (WRITE ENABLE) • 10H (PROGRAM EXECUTE)

• 0FH (GET FEATURE command to read the status) • 13H (PAGE READ to cache)

Gigadevice developed the SPI NAND flash family with the preliminary idea of the migration in mind. The SPI NAND flash can also be used in domain of SPI NOR flash. This document will outline the product differences that attention will be required to facilitate the migration from SPI NOR flash. This document discusses the use of SPI NAND flash from 512Mbit to 4Gbit density.

2.1 Density:

The SPI NAND flash family will be available in monolithic 512Mbit, 1Gbit, 2Gbit, 4Gbit densities.

2.2 Block architecture

The SPI NAND flash has a 128K + 4K bytes block which includes 64 pages for erase. Each page has 2K-bytes + 64-bytes spare area for program and read.

2.3 Secure Silicon OTP Area:

The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages (2112 bytes per page) are available on the device. Customers can use the OTP area any way they want, like programming serial numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP_PRT is 0.

2.4 Command:

The page program and page read commands need to pay attention to, the difference from that of SPI NOR flash. Both commands contain several steps, described as follows. Program command:

G Page Read command:

• 0FH (GET FEATURES command to read the status) cache dual IO)/EBH (Read from cache quad IO)

• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH (Read from

2.5 Prohibited blocks:

Some blocks are reserved for security consideration. So operations to these blocks are prohibited.

Note: For 1Gbit: block 1024~1021. For 2Gbit: block 2048~2045.

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SPI(x1/x2/x4) NAND Flash GD5FFMQ4UAYIG GD5F1GQ4UAYIG GD5F2GQ4UAYIG GD5F4GQ4UAYIG Application Note

For 4Gbit: block 2048~2045. Others: No prohibition.

DPr Celoimnfinidearnytial 3. Boot from SPI NAND Flash: 4. Bad Block :

5. Read Disturb Definition:

Write/Erase

Cycles [Cycles]

Estimated Read Cycles per page

[Cycles]

100,000

Initial

(less than 100)

50,000 10,000 2

The data of page 0 in block 0 will be automatically read to cache during power up sequence. So a random read command (03H/0BH) similar to SPI NOR flash could be used to access the page 0 in block 0 for boot operation.

SPI NAND Flash devices are shipped from the factory with invalid blocks with the Bad Block Mark (00h) to byte 2048 in the first page in each bad block. The recommended method to scan the initial bad blocks is show in the following figure.

During the life time, new bad block will appear when a P_FAIL/E_FAIL in the status register is set to high.

GLike the parallel interface NAND flash, SPI NAND flash has read cycling limits either. So limited read cycles are defined as follows:

SPI(x1/x2/x4) NAND Flash GD5FFMQ4UAYIG GD5F1GQ4UAYIG GD5F2GQ4UAYIG GD5F4GQ4UAYIG Application Note - If the number of W/E cycling < 100, the read cycle per page allowed is 100K. - If the number of W/E cycling < 50k, the read cycle per page allowed is 10K.

DPr Celoimnfinidearnytial 6. Appendix status register:

Protection A0H BRWD

Reserved BP2

BP1

BP0

INV

CMP

Feature B0H OTP_PRT OTP_EN

Reserved

ECC_EN

Reserved

Reserved Reserved QE

Register Addr. 7 6 5 4 3 2 1 0 Reserved

Status C0H Reserved Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP

Description:

Bit Bit Name Description

Fail

P_FAIL Program This bit indicates that a program failure has occurred (P_FAIL set to 1). It will also be

set if the user attempts to program an invalid address or a protected region, including the OTP area. This bit is cleared during the PROGRAM EXECUTE command sequence or a RESET command (P_FAIL = 0).

This bit indicates that an erase failure has occurred (E_FAIL set to 1). It will also be

E_FAIL Erase Fail

set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at the start of the BLOCK ERASE command sequence or the RESET command.

This bit indicates the current status of the write enable latch (WEL) and must be set WEL Write Enable Latch

(WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing the WRITE DISABLE command.

OIP Operation This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, BLOCK

In Progress

ERASE, or RESET command is executing, indicating the device is busy. When the bit is 0, the interface is in the ready state. ECCS provides ECC status as follows:

ECCS1,ECCS0 ECC Status

G

00b = No bit errors were detected during the previous read algorithm. 01b = bit error was detected and corrected, error bit number = 1~7. 10b = bit error was detected and not corrected.

11b = bit error was detected and corrected, error bit number = 8.

ECCS is set to 00b either following a RESET, or at the beginning of the READ. It is then updated after the device completes a valid READ operation. ECC_EN to 0).

ECCS is invalid if internal ECC is disabled (via a SET FEATURES command to reset After power-on RESET, ECC status is set to reflect the contents of block 0, page 0.

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SPI(x1/x2/x4) NAND Flash GD5FFMQ4UAYIG GD5F1GQ4UAYIG GD5F2GQ4UAYIG GD5F4GQ4UAYIG Application Note REVISION HISTORY

Version No

1.0 1.1

DPr Celoimnfinidearnytial Description

Date

Initial Release

Mar 20, 2013 May 5, 2013

Change P/E cycles

G 4