MM74HC4046

MM74HC4046

CMOS Phase Lock Loop

General Description

The MM74HC4046 is a low power phase lock loop utilizingadvanced silicon-gate CMOS technology to obtain high fre-quency operation both in the phase comparator and VCOsections. This device contains a low power linear voltagecontrolled oscillator (VCO), a source follower, and threephase comparators. The three phase comparators have acommon signal input and a common comparator input. Thesignal input has a self biasing amplifier allowing signals tobe either capacitively coupled to the phase comparatorswith a small signal or directly coupled with standard inputlogic levels. This device is similar to the CD4046 exceptthat the Zener diode of the metal gate CMOS device hasbeen replaced with a third phase comparator.

Phase Comparator I is an exclusive OR (XOR) gate. It pro-vides a digital error signal that maintains a 90 phase shiftbetween the VCO’s center frequency and the input signal(50% duty cycle input waveforms). This phase detector ismore susceptible to locking onto harmonics of the input fre-quency than phase comparator I, but provides better noiserejection.

Phase comparator III is an SR flip-flop gate. It can be usedto provide the phase comparator functions and is similar tothe first comparator in performance.

Phase comparator II is an edge sensitive digital sequentialnetwork. Two signal outputs are provided, a comparatoroutput and a phase pulse output. The comparator output isa 3-STATE output that provides a signal that locks the VCOoutput signal to the input signal with 0 phase shift between

them. This comparator is more susceptible to noise throw-ing the loop out of lock, but is less likely to lock onto har-monics than the other two comparators.

In a typical application any one of the three comparatorsfeed an external filter network which in turn feeds the VCOinput. This input is a very high impedance CMOS inputwhich also drives the source follower. The VCO’s operatingfrequency is set by three external components connectedto the C1A, C1B, R1 and R2 pins. An inhibit pin is providedto disable the VCO and the source follower, providing amethod of putting the IC in a low power state.

The source follower is a MOS transistor whose gate is con-nected to the VCO input and whose drain connects theDemodulator output. This output normally is used by tyinga resistor from pin 10 to ground, and provides a means oflooking at the VCO input without loading down modifyingthe characteristics of the PLL filter.

Features

sLow dynamic power consumption: (VCC = 4.5V)sMaximum VCO operating frequency:12 MHz (VCC = 4.5V)sFast comparator response time (VCC = 4.5V)

Comparator I:Comparator II:Comparator III:

25 ns30 ns25 ns

sVCO has high linearity and high temperature stability

Ordering Code:

Order NumberMM74HC4046MMM74HC4046SJMM74HC4046MTCMM74HC4046N

Package Number

M16AM16DMTC16N16E

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

© 2003 Fairchild Semiconductor CorporationDS005352www.fairchildsemi.com

MM74HC4046Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Block Diagram

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MM74HC4046Absolute Maximum Ratings(Note 1)

(Note 2)

Supply Voltage (VCC)DC Input Voltage (VIN)DC Output Voltage (VOUT)Clamp Diode Current (IIK, IOK)DC Output Current per pin (IOUT)DC VCC or GND Current, per pin (ICC)Storage Temperature Range (TSTG)Power Dissipation (PD)(Note 3)

S.O. Package onlyLead Temperature (TL)(Soldering 10 seconds)

260°C600 mW500 mW

Recommended OperatingConditions

Min

Supply Voltage (VCC)DC Input or Output Voltage(VIN, VOUT)

Operating Temperature Range (TA)Input Rise or Fall Times(tr, tf) VCC = 2.0V

VCC = 4.5VVCC = 6.0V

1000500400

nsnsns

0

VCC

V

2

Max6

UnitsV

−0.5 to + 7.0V−1.5 to VCC +1.5V−0.5 to VCC + 0.5V

±20 mA±25 mA±50 mA−65°C +150°C

−40+85°C

Note 1: Maximum Ratings are those values beyond which damage to thedevice may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.Note 3: Power Dissipation temperature derating — plastic “N” package: −12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

SymbolVIH

Parameter

Minimum HIGH Level Input Voltage

VIL

Maximum LOW Level Input Voltage

VOH

Minimum HIGH Level Output Voltage

VIN = VIH or VIL|IOUT| ≤ 20 µA

2.0V4.5V6.0V

VIN = VIH or VIL|IOUT| ≤ 4.0 mA|IOUT| ≤ 5.2 mA

VOL

Maximum Low Level Output Voltage

VIN = VIHor VIL|IOUT| ≤ 20 µA

2.0V4.5V6.0V

VIN = VIH or VIL|IOUT| ≤ 4.0 mA|IOUT| ≤ 5.2 mA

IINIINIOZICC

Maximum Input Current (Pins 3,5,9)VIN = VCCor GNDMaximum Input Current (Pin 14)Maximum 3-STATE OutputLeakage Current (Pin 13)Maximum Quiescent Supply Current

VIN = VCC or GNDIOUT = 0 µAVIN = VCC or GNDPin 14 Open

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used whendesigning with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

ConditionsVCC2.0V4.5V6.0V2.0V4.5V6.0V

TA = 25°CTyp

1.53.1.20.51.351.8

2.04.56.04.25.70000.20.220

1.94.45.93.985.480.10.10.10.260.26±0.150±0.5

30600

801500

TA = −40 to 85°CTA = −55 to 125°CGuaranteed Limits

1.53.1.20.51.351.81.94.45.93.845.340.10.10.10.330.33±1.080±5.01302400

1.53.1.20.51.351.81.94.45.93.75.20.10.10.10.40.4±1.0100±101603000

UnitsVVVVVVVVVVVVVVVVµAµAµAµAµA

4.5V6.0V

4.5V6.0V6.0V6.0V6.0V6.0V6.0V

VIN = VCC or GNDVOUT = VCC or GND

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MM74HC4046AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tr = 6 ns (unless otherwise specified.)

Symbol

Parameters

AC CoupledInput Sensitivity,Signal In

tr, tf

Maximum OutputRise and Fall Time

CIN

Maximum Input Capacitance

ConditionsC (series) = 100 pFfIN = 500 kHz

VCC2.0V4.5V6.0V2.0V4.5V6.0V7

6525207525228830259032281003427752522130

2004034225382404841240484125050432004034

2505043280583006051300605131063532505043

3006051340685736072613607261380753006051

Phase Comparator I

tPHL, tPLHMaximum 2.0VPropagation Delay

Phase Comparator IItPZL

Maximum 3-STATEEnable Time

tPZH, tPHZMaximum 3-STATE

Enable Time

tPLZ

Maximum 3-STATEDisable Time

2.0V4.5V6.0V2.0V4.5V6.0V2.0V4.5V6.0V

tPHL, tPLHMaximum 2.0VPropagation Delay

HIGH-to-LOW to Phase Pulses

Phase Comparator III

tPHL, tPLHMaximum 2.0VPropagation Delay

CPD

Maximum PowerDissipation Capacitance

All ComparatorsVIN = VCC and GND

4.5V6.0V

nsnsnspF

4.5V6.0V

nsnsnsnsnsnsnsnsnsnsnsns

4.5V6.0V

nsnsns

TA=25CTyp25501353098

100150250751512

TA = −40 to 85°CTA = −55 to 125°CGuaranteed Limits

150200300951915

2002503501102219

UnitsmVmVmVnsnsnspF

Voltage Controlled Oscillator (Specified to operate from VCC= 3.0V to 6.0V)fMAX

MaximumOperatingFrequency

C1 = 50 pFR1 = 100ΩR2 = ∞VCOin = VCCC1 = 0 pFR1 = 100ΩVCOin = VCC

Duty Cycle

Demodulator Output

Offset VoltageVCOin–VdemOffsetVariation

Rs = 20 kΩVCOin = 1.75V2.25V2.75V

4.5V

0.650.10.75

V

Rs = 20 kΩ

4.5V

0.75

1.3

1.5

1.6

V

50

%

4.5V6.0

1214

MHzMHz

4.5V6.0V

711

4.57

MHzMHz

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MM74HC4046Typical Performance Characteristics

Typical Center Frequencyvs R1, C1VCC = 4.5V

Typical Center Frequencyvs R1, C1VCC = 6V

Typical Offset Frequencyvs R2, C1VCC = 4.5V

Typical Offset Frequencyvs R2, C1VCC = 6V

Typical VCO Power Dissipation@ Center Frequency vs R1

Typical VCO PowerDissipation @ fMIN vs R2

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MM74HC4046Typical Performance Characteristics (Continued)

VCOin vs fout

VCC = 4.5V

VCOin vs foutVCC = 4.5V

VCOout vs

TemperatureVCC = 4.5V

VCOout vs

TemperatureVCC = 6V

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MM74HC4046Typical Performance Characteristics (Continued)

HC4046 Typical Source Follower

Power Dissipation vs RS

Typical fMAX/fMIN vs R2/R1VCC = 4.5V & 6V fMAX/fMIN

Typical VCO Linaearity vs R1 & C1

Typical VCO Linearity vs R1 & C1

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MM74HC4046Detailed Circuit Description

VOLTAGE CONTROLLED OSCILLATOR/SOURCEFOLLOWER

The VCO requires two or three external components tooperate. These are R1, R2, C1. Resistor R1 and capacitorC1 are selected to determine the center frequency of theVCO. R1 controls the lock range. As R1’s resistancedecreases the range of fMIN to fMAX increases. Thus theVCO’s gain increases. As C1 is changed the offset (if used)of R2, and the center frequency is changed. (See typicalperformance curves) R2 can be used to set the offset fre-quency with 0V at VCO input. If R2 is omitted the VCOrange is from 0Hz. As R2 is decreased the offset frequencyis increased. The effect of R2 is shown in the design infor-mation table and typical performance curves. By increasing

the value of R2 the lock range of the PLL is offset above0Hz and the gain (Hz/Volt) does not change. In general,when offset is desired, R2 and C1 should be chosen first,and then R1 should be chosen to obtain the proper centerfrequency.

Internally the resistors set a current in a current mirror asshown in Figure 1. The mirrored current drives one side ofthe capacitor once the capacitor charges up to the thresh-old of the schmitt trigger the oscillator logic flips the capaci-tor over and causes the mirror to charge the opposite sideof the capacitor. The output from the internal logic is thentaken to pin 4.

VCO WITHOUT OFFSET

R2 = ∞

VCO WITH OFFSET

Comparator IR2= ∞

•Given: f0

•Use f0 with curve titledcenter frequency vs R1, Cto determine R1 and C1

R2≠∞

•Given: f0 and fL

•Calculate fMIN from the equation fMIN = fo − fL•Use fMIN with curve titledoffset frequency vs R2, Cto determine R2 and C1•Calculate fMAX/fMIN fromthe equation fMAX/fMIN =fo + fL/fo − fL

•Use fMAX/fMIN with curvetitled fMAX/fMIN vs R2/R1to determine ratio R2/R1to obtain R1

FIGURE 1.

R2= ∞

•Given: fMAX

Comparator II & IIIR2≠∞

•Given: fMIN and fMAX•Use fMIN with curve titledoffset frequency vs R2,C to determine R2 and C1•Calculate fMAX/fMIN•Use fMAX/fMIN with curvetitled fMAX/fMIN vs R2/R1to determine ratio R2/R1to obtain R1

•Calculate f0 from theequation fo = fMAX/2•Use f0 with curve titledcenter frequency vs R1, Cto determine R1 and C1

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MM74HC4046Detailed Circuit Description (Continued)

FIGURE 2. Logic Diagram for VCO

not being used. A logic high on inhibit disables the VCOThe input to the VCO is a very high impedance CMOS

and source follower.input and so it will not load down the loop filter, easing the

filters design. In order to make signals at the VCO inputThe output of the VCO is a standard high speed CMOSaccessible without degrading the loop performance aoutput with an equivalent LSTTL fanout of 10. The VCOsource follower transistor is provided. This transistor canoutput is approximately a square wave. This output canbe used by connecting a resistor to ground and its draineither directly feed the comparator input of the phase com-output will follow the VCO input signal.parators or feed external prescalers (counters) to enable

frequency synthesis.An inhibit signal is provided to allow disabling of the VCO

and the source follower. This is useful if the internal VCO isPHASE COMPARATORS

All three phase comparators share two inputs, Signal Inand Comparator In. The Signal In has a special DC biasnetwork that enables AC coupling of input signals. If thesignals are not AC coupled then this input requires logiclevels the same as standard 74HC. The Comparator input

is a standard digital input. Both input structures are shownin Figure 3.

The outputs of these comparators are essentially standard74HC voltage outputs. (Comparator II is 3-STATE.)

FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators

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MM74HC4046Detailed Circuit Description (Continued)

FIGURE 4. Typical Phase Comparator I. Waveforms

Thus in normal operation VCC and ground voltage levelsare fed to the loop filter. This differs from some phasedetectors which supply a current output to the loop filterand this should be considered in the design. (The CD4046also provides a voltage.)

Figure 5 shows the state tables for all three comparators.PHASE COMPARATOR I

This comparator is a simple XOR gate similar to the74HC86, and its operation is similar to an overdriven bal-anced modulator. To maximize lock range the input fre-quencies must have a 50% duty cycle. Typical input andoutput waveforms are shown in Figure 4. The output of thephase detector feeds the loop filter which averages the out-put voltage. The frequency range upon which the PLL willlock onto if initially out of lock is defined as the capturerange. The capture range for phase detector I is dependenton the loop filter employed. The capture range can be aslarge as the lock range which is equal to the VCO fre-quency range.

To see how the detector operates refer to Figure 4. Whentwo square wave inputs are applied to this comparator, anoutput waveform whose duty cycle is dependent on thephase difference between the two signals results. As thephase difference increases the output duty cycle increasesand the voltage after the loop filter increases. Thus in orderto achieve lock, when the PLL input frequency increasesthe VCO input voltage must increase and the phase differ-ence between comparator in and signal in will increase. Atan input frequency equal fMIN, the VCO input is at 0V andthis requires the phase detector output to be ground hencethe two input signals must be in phase. When the input fre-quency is fMAX then the VCO input must be VCC and thephase detector inputs must be 180° out of phase.

The XOR is more susceptible to locking onto harmonics ofthe signal input than the digital phase detector II. This canbe seen by noticing that a signal 2 times the VCO fre-quency results in the same output duty cycle as a signalequal the VCO frequency. The difference is that the outputfrequency of the 2f example is twice that of the other exam-ple. The loop filter and the VCO range should be designedto prevent locking on to harmonics.PHASE COMPARATOR II

This detector is a digital memory network. It consists of fourflip-flops and some gating logic, a three state output and aphase pulse output as shown in Figure 6. This comparatoracts only on the positive edges of the input signals and isthus independent of signal duty cycle.

Phase comparator II operates in such a way as to force thePLL into lock with 0 phase difference between the VCOoutput and the signal input positive waveform edges. Fig-ure 7 shows some typical loop waveforms. First assumethat the signal input phase is leading the comparator input.This means that the VCO’s frequency must be increased tobring its leading edge into proper phase alignment. Thusthe phase detector II output is set high. This will cause theloop filter to charge up the VCO input increasing the VCOfrequency. Once the leading edge of the comparator inputis detected the output goes 3-STATE holding the VCOinput at the loop filter voltage. If the VCO still lags the sig-nal then the phase detector will again charge up to VCOinput for the time between the leading edges of both wave-forms.

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MM74HC4046Detailed Circuit Description (Continued)

Phase Comparator State Diagrams

FIGURE 5. PLL State Tables

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MM74HC4046Detailed Circuit Description (Continued)

FIGURE 6. Logic Diagram for Phase Comparator II

FIGURE 7. Typical Phase Comparator II Output Waveforms

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MM74HC4046Detailed Circuit Description (Continued)

If the VCO leads the signal then when the leading edge ofthe VCO is seen the output of the phase comparator goesLOW. This discharges the loop filter until the leading edgeof the signal is detected at which time the output 3-STATEitself again. This has the effect of slowing down the VCO toagain make the rising edges of both waveform coincident.When the PLL is out of lock the VCO will be running eitherslower or faster than the signal input. If it is running slowerthe phase detector will see more signal rising edges and sothe output of the phase comparator will be HIGH a majorityof the time, raising the VCO’s frequency. Conversely, if theVCO is running faster than the signal the output of thedetector will be LOW most of the time and the VCO’s out-put frequency will be decreased.

As one can see when the PLL is locked the output of phasecomparator II will be almost always 3-STATE except forminor corrections at the leading edge of the waveforms.When the detector is 3-STATE the phase pulse output isHIGH. This output can be used to determine when the PLLis in the locked condition.

This detector has several interesting characteristics. Overthe entire VCO frequency range there is no phase differ-ence between the comparator input and the signal input.The lock range of the PLL is the same as the capturerange. Minimal power is consumed in the loop filter since inlock the detector output is a high impedance. Also when nosignal is present the detector will see only VCO leadingedges, and so the comparator output will stay LOW forcingthe VCO to fMIN operating frequency.

Phase comparator II is more susceptible to noise causingthe phase lock loop to unlock. If a noise pulse is seen onthe signal input, the comparator treats it as another positiveedge of the signal and will cause the output to go HIGHuntil the VCO leading edge is seen, potentially for a wholesignal input period. This would cause the VCO to speed upduring that time. When using the phase comparator I theoutput of that phase detector would be disturbed for onlythe short duration of the noise spike and would cause lessupset.

PHASE COMPARATOR III

This comparator is a simple S-R Flip-Flop which can func-tion as a phase comparator Figure 8. It has some similarcharacteristics to the edge sensitive comparator. To seehow this detector works assume input pulses are applied tothe signal and comparator inputs as shown in Figure 9.When the signal input leads the comparator input the flop isset. This will charge up the loop filter and cause the VCO tospeed up, bringing the comparator into phase with the sig-nal input. When using short pulses as input this comparatorbehaves very similar to the second comparator. But onecan see that if the signal input is a long pulse, the output ofthe comparator will be forced to a one no matter how manycomparator input pulses are received. Also if the VCO inputis a square wave (as it is) and the signal input is pulse thenthe VCO will force the comparator output LOW much of thetime. Therefore it is ideal to condition the signal and com-parator input to short pulses. This is most easily done byusing a series capacitor.

FIGURE 8. Phase Comparator III Logic Diagram

FIGURE 9. Typical Waveforms for Phase Comparator III

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MM74HC4046Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150\" Narrow

Package Number M16A

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MM74HC4046Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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MM74HC4046Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

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MM74HC4046 CMOS Phase Lock LoopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300\" Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

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