EDA课程设计,北华航天工业学院,计数器及数码显示(一)

60进制计数器异步清零同步预置数程序 libraryieee;

use ieee.std_logic_11.all; useieee.std_logic_arith.all;

useieee.std_logic_unsigned.all; entity counter60 is

port(clk,en,rst,load:instd_logic; din:instd_logic_vector(7 downto 0); co:outstd_logic;

qh,ql:bufferstd_logic_vector(3 downto 0) );

end counter60;

architecture one of counter60 is begin

co<='1'when(qh=\"0101\"and ql=\"1001\"and en='1')else'0'; process(clk,rst) begin

if(rst='0')then qh<=\"0000\"; ql<=\"0000\";

elsif(clk'event and clk='1')then if(load='1')then

qh<=din(7 downto 4); ql<=din(3 downto 0); elsif(en='1')then if(ql=9)then ql<=\"0000\";

if(qh=5)then qh<=\"0000\"; else

qh<=qh+1; end if; else

ql<=ql+1; end if; end if; end if;

end process; end one;

时间扫描模块 libraryieee;

use ieee.std_logic_11.all; useieee.std_logic_unsigned.all; entity seltime is

port(clk: in bit;

qhin,qlin: in std_logic_vector(3 downto 0); sel: out std_logic_vector(2 downto 0); daout: out std_logic_vector(3 downto 0)); endseltime;

architecture a of seltime is

signaltemp:integer range 0 to 1; begin

process(clk) begin

if (clk'event and clk='1') then if temp=1 then temp<=0; else temp<=temp + 1; end if; case temp is

when 0=>sel<=\"000\";daout<=qlin; when 1=>sel<=\"001\";daout<=qhin; end case; end if;

end process; end a;

共阴7段数码管

library IEEE;

use IEEE.STD_LOGIC_11.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity deled is

Port (din:instd_logic_vector(3 downto 0 ); ledout:outstd_logic_vector(6 downto 0) ); end deled;

architecture three of deled is begin

process(din) begin case din is

when\"0000\"=>ledout<=\"0111111\";--0 when\"0001\"=>ledout<=\"0000110\";--1 when\"0010\"=>ledout<=\"1011011\";--2 when\"0011\"=>ledout<=\"1001111\";--3 when\"0100\"=>ledout<=\"1100110\"; --4 when\"0101\"=>ledout<=\"1101101\";--5 when\"0110\"=>ledout<=\"1111101\";--6 when\"0111\"=>ledout<=\"0100111\";--7 when\"1000\"=>ledout<=\"1111111\";--8 when\"1001\"=>ledout<=\"1101111\";--9 when others =>ledout<=\"0000000\"; end case; end process; end three;