ADC104S051资料

ADC104S1014Channel,1MSPS,10-BitA/DConverterMay2005

ADC104S101

4Channel,1MSPS,10-BitA/DConverter

GeneralDescription

TheADC104S101isalow-power,four-channelCMOS10-bitanalog-to-digitalconverterwithahigh-speedserialinterface.Unliketheconventionalpracticeofspecifyingperformanceatasinglesamplerateonly,theADC104S101isfullyspeci-fiedoverasampleraterangeof500kSPSto1MSPS.Theconverterisbasedonasuccessive-approximationregisterarchitecturewithaninternaltrack-and-holdcircuit.ItcanbeconfiguredtoacceptuptofourinputsignalsatinputsIN1throughIN4.

Theoutputserialdataisstraightbinary,andiscompatiblewithseveralstandards,suchasSPI™,QSPI™,MICROW-IRE,andmanycommonDSPserialinterfaces.

TheADC104S101operateswithasinglesupply,thatcanrangefrom+2.7Vto+5.25V.Normalpowerconsumptionusinga+3Vor+5Vsupplyis3.9mWand11.4mW,respec-tively.Thepower-downfeaturereducesthepowerconsump-tiontojust0.12µWusinga+3.6Vsupply,or0.47µWusinga+5.5Vsupply.

TheADC104S101ispackagedina10-leadMSOPpackage.Operationovertheindustrialtemperaturerangeof−40˚Cto+85˚Cisguaranteed.

Features

nnnn

Specifiedoverarangeofsamplerates.Fourinputchannels

Variablepowermanagement

Singlepowersupplywith2.7V-5.25Vrange

KeySpecifications

nnnn

DNLINLSNR

PowerConsumption—3VSupply—5VSupply

+0.26/−0.16LSB(typ)+0.4/−0.1LSB(typ)

61.7dB(typ)

3.9mW(typ)11.4mW(typ)

Applications

nPortableSystems

nRemoteDataAcquisition

nInstrumentationandControlSystems

Pin-CompatibleAlternativesbyResolutionandSpeed

Alldevicesarefullypinandfunctioncompatible.

Resolution

50to200kSPS

12-bit10-bit8-bit

ADC124S021ADC104S021ADC084S021

SpecifiedforSampleRatesof:

200to500kSPSADC124S051ADC104S051ADC084S051

500kSPSto1MSPS

ADC124S101ADC104S101ADC084S101

ConnectionDiagram

20125005

TRI-STATE®isatrademarkofNationalSemiconductorCorporationQSPI™andSPI™aretrademarksofMotorola,Inc.

©2005NationalSemiconductorCorporationDS201250www.national.com

元器件交易网www.cecb2b.com

ADC104S101OrderingInformation

OrderCodeADC104S101CIMMADC104S101CIMMXADC104S101EVAL

TemperatureRange−40˚Cto+85˚C−40˚Cto+85˚C

Description10-LeadMSOPPackage

10-LeadMSOPPackage,Tape&Reel

EvaluationBoard

TopMarkX26CX26C

BlockDiagram

20125007

PinDescriptionsandEquivalentCircuits

PinNo.ANALOGI/O

4-7DIGITALI/O

10981

POWERSUPPLY

Positivesupplypin.Thispinshouldbeconnectedtoaquiet+2.7Vto+5.25VsourceandbypassedtoGNDwitha1µFcapacitoranda0.1µFmonolithiccapacitorlocatedwithin1cmofthepowerpin.

Thegroundreturnfortheanalogsupplyandsignals.

SCLKDOUTDINCS

Digitalclockinput.Thisclockdirectlycontrolstheconversionandreadoutprocesses.

Digitaldataoutput.TheoutputsamplesareclockedoutofthispinonfallingedgesoftheSCLKpin.

Digitaldatainput.TheADC104S101’sControlRegisterisloadedthroughthispinonrisingedgesoftheSCLKpin.Chipselect.OnthefallingedgeofCS,aconversionprocessbegins.ConversionscontinueaslongasCSisheldlow.

IN1toIN4

Analoginputs.Thesesignalscanrangefrom0VtoVA.

Symbol

Description

2

VA3GND

www.national.com2

元器件交易网www.cecb2b.com

ADC104S101AbsoluteMaximumRatings(Notes1,2)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.SupplyVoltageVAVoltageonAnyPintoGNDInputCurrentatAnyPin(Note3)PackageInputCurrent(Note3)PowerConsumptionatTA=25˚CESDSusceptibility(Note5)HumanBodyModelMachineModelJunctionTemperatureStorageTemperature

−0.3Vto6.5V−0.3VtoVA+0.3V

OperatingRatings(Notes1,2)

OperatingTemperatureRangeVASupplyVoltage

DigitalInputPinsVoltageRangeClockFrequencyAnalogInputVoltage

−40˚C≤TA≤+85˚C

+2.7Vto+5.25V

−0.3VtoVA0.8MHzto16MHz

0VtoVA±10mA±20mA

See(Note4)

2500V250V+150˚C

−65˚Cto+150˚C

PackageThermalResistance

Package10-leadMSOP

θJA190˚C/W

SolderingprocessmustcomplywithNationalSemiconduc-tor’sReflowTemperatureProfilespecifications.Refertowww.national.com/packaging.(Note6)

(Note9)

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=8MHzto16MHz,

fSAMPLE=500kSPSto1MSPS,unlessotherwisenoted.BoldfacelimitsapplyforTA=TMINtoTMAX;allotherlimitsTA=25˚C.Symbol

Parameter

Conditions

Typical

Limits(Note7)10

+0.4−0.1+0.26−0.16+0.190.02−0.150.02

+0.7−0.5+0.6−0.6

Units

ADC104S101ConverterElectricalCharacteristics

STATICCONVERTERCHARACTERISTICS

ResolutionwithNoMissingCodes

INLDNLVOFFOEMFSEFSEM

IntegralNon-LinearityDifferentialNon-LinearityOffsetError

ChanneltoChannelOffsetErrorMatchFull_ScaleError

ChanneltoChannelFull_ScaleErrorMatch

VA=+2.7Vto5.25V

fIN=40.3kHz,−0.02dBFSVA=+2.7Vto5.25V

fIN=40.3kHz,−0.02dBFSVA=+2.7Vto5.25V

fIN=40.3kHz,−0.02dBFSVA=+2.7Vto5.25V

fIN=40.3kHz,−0.02dBFSVA=+2.7Vto5.25V

fIN=40.3kHz,−0.02dBFSVA=+5.25VfIN=40.3kHz

VA=+5.25V

fa=40.161kHz,fb=41.015kHzVA=+5.25V

fa=40.161kHz,fb=41.015kHzVA=+5VVA=+3V

BitsLSB(max)LSB(min)LSB(max)LSB(min)LSB(max)LSB(max)LSB(max)LSB(max)

±0.6±0.6±0.7±0.5

DYNAMICCONVERTERCHARACTERISTICSSINADSNRTHDSFDRENOB

Signal-to-NoisePlusDistortionRatioSignal-to-NoiseRatioTotalHarmonicDistortionSpurious-FreeDynamicRangeEffectiveNumberofBitsChannel-to-ChannelCrosstalk

IntermodulationDistortion,SecondOrderTerms

IntermodulationDistortion,ThirdOrderTerms

-3dBFullPowerBandwidth

61.661.7−82839.9−78−82−81118

6161.3−72759.8

dB(min)dB(min)dB(max)dB(min)Bits(min)

dBdBdBMHzMHz

IMD

FPBW

3www.national.com

元器件交易网www.cecb2b.com

ADC104S101ADC104S101ConverterElectricalCharacteristics

(Note9)(Continued)

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=8MHzto16MHz,

fSAMPLE=500kSPSto1MSPS,unlessotherwisenoted.BoldfacelimitsapplyforTA=TMINtoTMAX;allotherlimitsTA=25˚C.

Parameter

Conditions

Typical

Limits(Note7)

Units

Symbol

ANALOGINPUTCHARACTERISTICSVINIDCLCINAInputRangeDCLeakageCurrentInputCapacitance

TrackModeHoldModeVA=+5.25VVA=+3.6VVIN=0VorVA333

2.42.10.8

0toVAV

±1

µA(max)pFpFV(min)V(min)V(max)µA(max)pF(max)V(min)VV(max)V

DIGITALINPUTCHARACTERISTICSVIHVILIINCINDInputHighVoltageInputLowVoltageInputCurrent

DigitalInputCapacitance

ISOURCE=200µAISOURCE=1mAISINK=200µAISINK=1mA

±0.2

2VA−0.03VA−0.10.030.1

±10

4VA−0.50.4

DIGITALOUTPUTCHARACTERISTICSVOHVOLIOZH,IOZLCOUTOutputHighVoltageOutputLowVoltage

TRI-STATE®LeakageCurrentTRI-STATE®OutputCapacitanceOutputCoding

POWERSUPPLYCHARACTERISTICS(CL=10pF)VASupplyVoltage

VA=+5.25V,

fSAMPLE=1MSPS,fIN=40kHzVA=+3.6V,

fSAMPLE=1MSPS,fIN=40kHzVA=+5.25V,

fSAMPLE=0kSPSVA=+3.6V,

fSAMPLE=0kSPSVA=+5.25VVA=+3.6VVA=+5.25VVA=+3.6V

2.181.08903311.43.90.470.12

816500113

fCLK=16MHzFull-ScaleStepInput

AcquisitionTime+ConversionTime

50

307031614.24.72.75.252.71.3

V(min)V(max)mA(max)mA(max)

nAnAmW(max)mW(max)

µWµWMHz(min)MHz(max)kSPS(min)MSPS(max)SCLKcycles%(min)%(max)SCLKcyclesSCLKcycles

±0.01

2

±1

4

µA(max)pF(max)

Straight(Natural)Binary

SupplyCurrent,NormalMode(Operational,CSlow)

IASupplyCurrent,Shutdown(CShigh)

PDPowerConsumption,NormalMode(Operational,CSlow)

PowerConsumption,Shutdown(CShigh)

ACELECTRICALCHARACTERISTICSfSCLKfStCONVDCtACQClockFrequencySampleRateConversionTimeSCLKDutyCycle

Track/HoldAcquisitionTimeThroughputTime

(Note8)(Note8)

www.national.com4

元器件交易网www.cecb2b.com

ADC104S101ADC104S101TimingSpecifications

ThefollowingspecificationsapplyforVA=+2.7Vto5.25V,GND=0V,CL=50pF,fSCLK=8MHzto16MHz,fSAMPLE=500kSPSto1MSPS,BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25˚C.SymboltCSUtCLHtENtACCtSUtHtCHtCLParameter

SetupTimeSCLKHightoCSFallingEdgeHoldtimeSCLKLowtoCSFallingEdgeDelayfromCSUntilDOUTactive

DataAccessTimeafterSCLKFallingEdgeDataSetupTimePriortoSCLKRisingEdgeDataValidSCLKHoldTimeSCLKHighPulseWidthSCLKLowPulseWidth

OutputFalling

tDISCSRisingEdgetoDOUTHigh-Impedance

OutputRising

VA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0V

(Note10)(Note10)

Conditions

VA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0VVA=+3.0VVA=+5.0V

Typical−3.5−0.5+4.5+1.5+4+2+16.5+15+3+30.5xtSCLK0.5xtSCLK1.71.21.01.0

20

ns(max)

Limits(Note7)1010303010100.3xtSCLK0.3xtSCLKUnitsns(min)ns(min)ns(max)ns(max)ns(min)ns(min)ns(min)ns(min)

Note1:AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotguaranteespecificperformancelimits.Forguaranteedspecificationsandtestconditions,seetheElectricalCharacteristics.Theguaranteedspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.

Note2:AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.

Note3:Whentheinputvoltageatanypinexceedsthepowersupply(thatis,VINVA),thecurrentatthatpinshouldbelimitedto10mA.The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof10mAtotwo.TheAbsoluteMaximumRatingspecificationdoesnotapplytotheVApin.ThecurrentintotheVApinislimitedbytheAnalogSupplyVoltagespecification.

Note4:Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150˚C.ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDMAX=(TJmax−TA)/θJA.Thevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.g.wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).Obviously,suchconditionsshouldalwaysbeavoided.

Note5:Humanbodymodelis100pFcapacitordischargedthrougha1.5kΩresistor.Machinemodelis220pFdischargedthroughzeroohms.Note6:Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.Note7:TestedlimitsareguaranteedtoNational’sAOQL(AverageOutgoingQualityLevel).

Note8:Thisisthefrequencyrangeoverwhichtheelectricalperformanceisguaranteed.ThedeviceisfunctionaloverawiderrangewhichisspecifiedunderOperatingRatings.

Note9:Datasheetmin/maxspecificationlimitsareguaranteedbydesign,test,orstatisticalanalysis.

Note10:Clockmaybeinanystate(highorlow)whenCSisasserted,withtherestrictionsonsetupandholdtimegivenbytCSUandtCLH.

5www.national.com

元器件交易网www.cecb2b.com

ADC104S101TimingDiagrams

20125008

TimingTestCircuit

20125051

ADC104S101OperationalTimingDiagram

20125006

ADC104S101SerialTimingDiagram

20125050

SCLKandCSTimingParameters

www.national.com6

元器件交易网www.cecb2b.com

ADC104S101SpecificationDefinitions

ACQUISITIONTIMEisthetimerequiredtoacquiretheinputvoltage.Thatis,itistimerequiredfortheholdcapacitortochargeuptotheinputvoltage.

APERTUREDELAYisthetimebetweenthefourthfallingSCLKedgeofaconversionandthetimewhentheinputsignalisacquiredorheldforconversion.

CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword.

CROSSTALKisthecouplingofenergyfromonechannelintotheotherchannel,ortheamountofsignalenergyfromoneanaloginputthatappearsatthemeasuredanaloginput.DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.Thespeci-ficationherereferstotheSCLK.

EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.ENOBisdefinedas(SINAD−1.76)/6.02andsaysthattheconverterisequiva-lenttoaperfectADCofthis(ENOB)numberofbits.FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.

GAINERRORisthedeviationofthelastcodetransition(111...110)to(111...111)fromtheideal(VREF−1.5LSB),afteradjustingforoffseterror.

INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(1⁄2LSBbelowthefirstcodetransition)throughpositivefullscale(1⁄2LSBabovethelastcodetransition).Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue.

INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalspectralcomponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.Itisdefinedastheratioofthepowerinthesecondandthirdorderintermodulationproductstothesumofthepowerinbothoftheoriginalfrequencies.IMDisusuallyexpressedindB.

MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.TheADC104S101isguaranteednottohaveanymissingcodes.

OFFSETERRORisthedeviationofthefirstcodetransition(000...000)to(000...001)fromtheideal(i.e.GND+0.5LSB).

SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingharmonicsord.c.

SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherspectralcompo-nentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.c.

SPURIOUSFREEDYNAMICRANGE(SFDR)isthediffer-ence,expressedindB,betweenthermsvaluesoftheinputsignalandthepeakspurioussignalwhereaspurioussignalisanysignalpresentintheoutputspectrumthatisnotpresentattheinput,excludingd.c.

TOTALHARMONICDISTORTION(THD)istheratio,ex-pressedindBordBc,ofthermstotalofthefirstfiveharmoniccomponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.THDiscalcu-latedas

whereAf1istheRMSpoweroftheinputfrequencyattheoutputandAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies.

THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwosuccessiveconversion.Itistheacquisitiontimeplustheconversiontime.InthecaseoftheADC104S101,thisis16SCLKperiods.

7www.national.com

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristics

fSCLK=8MHzto16MHz,fINDNL-VA=3.0V

TA=+25˚C,fSAMPLE=500kSPSto1MSPS,

=40.3kHzunlessotherwisestated.

INL-VA=3.0V

2012502020125021

DNL-VA=5.0VINL-VA=5.0V

2012506220125063

DNLvs.SupplyINLvs.Supply

2012502220125023

www.national.com8

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kSPSto1MSPS,

fSCLK=8MHzto16MHz,fIN=40.3kHzunlessotherwisestated.(Continued)

DNLvs.ClockFrequency

INLvs.ClockFrequency

2012502420125025

DNLvs.ClockDutyCycleINLvs.ClockDutyCycle

2012502620125027

DNLvs.TemperatureINLvs.Temperature

2012502820125029

9www.national.com

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kSPSto1MSPS,

fSCLK=8MHzto16MHz,fIN=40.3kHzunlessotherwisestated.(Continued)

SNRvs.Supply

THDvs.Supply

2012503020125035

SNRvs.ClockFrequencyTHDvs.ClockFrequency

2012503120125036

SNRvs.ClockDutyCycleTHDvs.ClockDutyCycle

2012503220125037

www.national.com10

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kSPSto1MSPS,

fSCLK=8MHzto16MHz,fIN=40.3kHzunlessotherwisestated.(Continued)

SNRvs.InputFrequency

THDvs.InputFrequency

2012503320125038

SNRvs.TemperatureTHDvs.Temperature

2012503420125039

SFDRvs.SupplySINADvs.Supply

2012504020125045

11www.national.com

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kSPSto1MSPS,

fSCLK=8MHzto16MHz,fIN=40.3kHzunlessotherwisestated.(Continued)

SFDRvs.ClockFrequency

SINADvs.ClockFrequency

2012504120125046

SFDRvs.ClockDutyCycleSINADvs.ClockDutyCycle

2012504220125047

SFDRvs.InputFrequencySINADvs.InputFrequency

2012504320125048

www.national.com12

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kSPSto1MSPS,

fSCLK=8MHzto16MHz,fIN=40.3kHzunlessotherwisestated.(Continued)

SFDRvs.Temperature

SINADvs.Temperature

2012504420125049

ENOBvs.SupplyENOBvs.ClockFrequency

2012505220125053

ENOBvs.ClockDutyCycleENOBvs.InputFrequency

2012505420125055

13www.national.com

元器件交易网www.cecb2b.com

ADC104S101TypicalPerformanceCharacteristicsTA=+25˚C,fSAMPLE=500kSPSto1MSPS,

fSCLK=8MHzto16MHz,fIN=40.3kHzunlessotherwisestated.(Continued)

ENOBvs.Temperature

SpectralResponse-3V,500kSPS

2012505620125064

SpectralResponse-5V,500kSPSSpectralResponse-3V,1.0MSPS

2012506520125059

SpectralResponse-5V,1.0MSPSPowerConsumptionvs.Throughput

2012506020125061

www.national.com14

元器件交易网www.cecb2b.com

ADC104S101ApplicationsInformation

1.0ADC104S101OPERATION

TheADC104S101isasuccessive-approximationanalog-to-digitalconverterdesignedaroundacharge-redistributiondigital-to-analogconverter.SimplifiedschematicsoftheADC104S101inbothtrackandholdmodesareshowninFigures1,2,respectively.InFigure1,theADC104S101isintrackmode:switchSW1connectsthesamplingcapacitortooneoffouranaloginputchannelsthroughthemultiplexer,andSW2balancesthecomparatorinputs.TheADC104S101isinthisstateforthefirstthreeSCLKcyclesafterCSisbroughtlow.

Figure2showstheADC104S101inholdmode:switchSW1connectsthesamplingcapacitortoground,mintainingthe

sampledvoltage,andswitchSW2unbalancesthecompara-tor.Thecontrollogictheninstructsthecharge-redistributionDACtoaddfixedamountsofchargetothesamplingcapaci-toruntilthecomparatorisbalanced.Whenthecomparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.TheADC104S101isinthisstateforthefourththroughsixteenthSCLKcyclesafterCSisbroughtlow.

ThetimewhenCSislowisconsideredaserialframe.Eachoftheseframesshouldcontainanintegermultipleof16SCLKcycles,duringwhichtimeaconversionisperformedandclockedoutattheDOUTpinanddataisclockedintotheDINpintoindicatethemultiplexeraddressforthenextconversion.

20125009

FIGURE1.ADC104S101inTrackMode

20125010

FIGURE2.ADC104S101inHoldMode

2.0USINGTHEADC104S101

AnADC104S101timingdiagramandaserialinterfacetimingdiagramfortheADC104S101areshownintheTimingDia-gramssection.CSischipselect,whichinitiatesconversionsandframestheserialdatatransfers.SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.DOUTistheserialdataoutputpin,whereaconversionresultissentasaserialdatastream,MSBfirst.DatatobewrittentotheADC104S101’sControlRegisterisplacedonDIN,theserialdatainputpin.NewdataiswrittentoDINwitheachconversion.

AserialframeisinitiatedonthefallingedgeofCSandendsontherisingedgeofCS.Eachframemustcontainanintegermultipleof16risingSCLKedges.TheADCoutputdata(DOUT)isinahighimpedancestatewhenCSishighandisactivewhenCSislow.Thus,CSactsasanoutputenable.Additionally,thedevicegoesintoapowerdownstatewhenCSishigh,andalsobetweencontinuousconversioncycles.

15

Duringthefirst3cyclesofSCLK,theADCisinthetrackmode,acquiringtheinputvoltage.Forthenext13SCLKcyclestheconversionisaccomplishedandthedataisclockedout,MSBfirst,startingonthe5thclock.Ifthereismorethanoneconversioninaframe,theADCwillre-enterthetrackmodeonthefallingedgeofSCLKaftertheN*16thrisingedgeofSCLK,andre-enterthehold/convertmodeontheN*16+4thfallingedgeofSCLK,where\"N\"isaninteger.WhenCSisbroughthigh,SCLKisinternallygatedoff.IfSCLKisstoppedinthelowstatewhileCSishigh,thesubsequentfallofCSwillgenerateafallingedgeoftheinternalversionofSCLK,puttingtheADCintothetrackmode.ThisisseenbytheADCasthefirstfallingedgeofSCLK.IfSCLKisstoppedwithSCLKhigh,theADCentersthetrackmodeonthefirstfallingedgeofSCLKafterthefallingedgeofCS.

Duringeachconversion,dataisclockedintotheDINpinonthefirst8risingedgesofSCLKafterthefallofCS.Foreach

www.national.com

元器件交易网www.cecb2b.com

ADC104S101ApplicationsInformation

(Continued)

conversion,itisnecessarytoclockinthedataindicatingtheinputthatisselectedfortheconversionafterthecurrentone.SeeTables1,2andTable3.

IfCSandSCLKgolowsimultaneously,itisthefollowingrisingedgeofSCLKthatisconsideredthefirstrisingedgeforclockingdataintoDIN.

Therearenopower-updelaysordummyconversionsre-quiredwiththeADC104S101.TheADCisabletosampleandconvertaninputtofullconversionimmediatelyfollowingpowerup.Thefirstconversionresultafterpower-upwillbethatofIN1.

TABLE1.ControlRegisterBits

Bit7(MSB)DONTC

Bit6DONTC

Bit5ADD2

Bit4ADD1

Bit3ADD0

Bit2DONTC

Bit1DONTC

Bit0DONTC

TABLE2.ControlRegisterBitDescriptions

Bit#:7-6,2-0

543

Symbol:DONTCADD2ADD1ADD0

Description

Don’tcare.Thevalueofthesebitsdonotaffectdeviceoperation.Thesethreebitsdeterminewhichinputchannelwillbesampledandconvertedinthenexttrack/holdcycle.ThemappingbetweencodesandchannelsisshowninTable3.

TABLE3.InputChannelSelectionADD2xxxx

ADD10011

ADD00101

InputChannelIN1(Default)

IN2IN3IN4

www.national.com16

元器件交易网www.cecb2b.com

ADC104S101ApplicationsInformation

3.0ADC104S101TRANSFERFUNCTION

(Continued)

TheoutputformatoftheADC104S101isstraightbinary.CodetransitionsoccurmidwaybetweensuccessiveintegerLSBvalues.TheLSBwidthfortheADC104S101isVA/1024.TheidealtransfercharacteristicisshowninFigure3.Thetransitionfromanoutputcodeof0000000000toacodeof0000000001isat1/2LSB,oravoltageofVA/2048.OthercodetransitionsoccuratstepsofoneLSB.

20125011

FIGURE3.IdealTransferCharacteristic

4.0TYPICALAPPLICATIONCIRCUIT

AtypicalapplicationoftheADC104S101isshowninFigure4.PowerisprovidedinthisexamplebytheNationalSemi-conductorLP2950low-dropoutvoltageregulator,availableinavarietyoffixedandadjustableoutputvoltages.ThepowersupplypinisbypassedwithacapacitornetworklocatedclosetotheADC104S101.BecausethereferencefortheADC104S101isthesupplyvoltage,anynoiseonthesupply

willdegradedevicenoiseperformance.Tokeepnoiseoffthesupply,useadedicatedlinearregulatorforthisdevice,orprovidesufficientdecouplingfromothercircuitrytokeepnoiseofftheADC104S101supplypin.BecauseoftheADC104S101’slowpowerrequirements,itisalsopossibletouseaprecisionreferenceasapowersupplytomaximizeperformance.Thefour-wireinterfaceisalsoshowncon-nectedtoamicroprocessororDSP.

20125013

FIGURE4.TypicalApplicationCircuit

17www.national.com

元器件交易网www.cecb2b.com

ADC104S101ApplicationsInformation

5.0ANALOGINPUTS

(Continued)

AnequivalentcircuitforoneoftheADC104S101’sinputchannelsisshowninFigure5.DiodesD1andD2provideESDprotectionfortheanaloginputs.Atnotimeshouldanyinputgobeyond(VA+300mV)or(GND-300mV),astheseESDdiodeswillbeginconducting,whichcouldresultinerraticoperation.

ThecapacitorC1inFigure5hasatypicalvalueof3pF,andismainlythepackagepincapacitance.ResistorR1istheonresistanceofthemultiplexerandtrack/holdswitch,andistypically500ohms.CapacitorC2istheADC104S101sam-plingcapacitor,andistypically30pF.TheADC104S101willdeliverbestperformancewhendrivenbyalow-impedancesourcetoeliminatedistortioncausedbythechargingofthesamplingcapacitance.ThisisespeciallyimportantwhenusingtheADC104S101tosampleACsignals.Alsoimportantwhensamplingdynamicsignalsisaband-passorlow-passfiltertoreduceharmonicsandnoise,improvingdynamicperformance.

Theusermaytradeoffthroughputforpowerconsumptionbysimplyperformingfewerconversionsperunittime.ThePowerConsumptionvs.SampleRatecurveintheTypicalPerformanceCurvessectionshowsthetypicalpowercon-sumptionoftheADC104S101versusthroughput.Tocalcu-latethepowerconsumption,simplymultiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumption,andaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerdissipation.7.1PowerManagement

WhentheADC104S101isoperatedcontinuouslyinnormalmode,themaximumthroughputisfSCLK/16.ThroughputmaybetradedforpowerconsumptionbyrunningfSCLKatitsmaximum16MHzandperformingfewerconversionsperunittime,puttingtheADC104S101intoshutdownmodebetweenconversions.AplotoftypicalpowerconsumptionversusthroughputisshownintheTypicalPerformanceCurvessection.Tocalculatethepowerconsumptionforagiventhroughput,multiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumptionandaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerconsumption.Generally,theuserwillputthepartintonormalmodeandthenputthepartbackintoshutdownmode.Notethatthecurveofpowerconsumptionvs.throughputisnearlylinear.Thisisbecausethepowerconsumptionintheshutdownmodeissosmallthatitcanbeignoredforallpracticalpurposes.

7.2PowerSupplyNoiseConsiderations

Thechargingofanyoutputloadcapacitancerequirescur-rentfromthepowersupply,VA.Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthesupply.Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.Furthermore,dischargingtheoutputcapaci-tancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresis-tive.Loaddischargecurrentswillcause\"groundbounce\"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.Thelargeristheoutputcapaci-tance,themorecurrentflowsthroughthediesubstrateandthegreateristhenoisecoupledintotheanalogchannel,degradingnoiseperformance.

Tokeepnoiseoutofthepowersupply,keeptheoutputloadcapacitanceassmallaspractical.Iftheloadcapacitanceisgreaterthan50pF,usea100ΩseriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandimprovenoiseperformance.

20125014

FIGURE5.EquivalentInputCircuit

6.0DIGITALINPUTSANDOUTPUTS

TheADC104S101’sdigitaloutputDOUTislimitedby,andcannotexceed,thesupplyvoltage,VA.Thedigitalinputpinsarenotpronetolatch-upand,andalthoughnotrecom-mended,SCLK,CSandDINmaybeassertedbeforeVAwithoutanylatch-uprisk.

7.0POWERSUPPLYCONSIDERATIONS

TheADC104S101isfullypowered-upwheneverCSislow,andfullypowered-downwheneverCSishigh,withoneexception:theADC104S101automaticallyenterspower-downmodebetweenthe16thfallingedgeofaconversionandthe1stfallingedgeofthesubsequentconversion(seeTimingDiagrams).

TheADC104S101canperformmultipleconversionsbacktoback;eachconversionrequires16SCLKcycles.TheADC104S101willperformconversionscontinuouslyaslongasCSisheldlow.

www.national.com18

元器件交易网www.cecb2b.com

ADC104S1014Channel,1MSPS,10-BitA/DConverterPhysicalDimensions

inches(millimeters)unlessotherwisenoted

10-LeadMSOP

OrderNumberADC104S101CIMM,ADC104S101CIMMX

NSPackageNumberP0MUB10A

Nationaldoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandNationalreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecifications.Forthemostcurrentproductinformationvisitusatwww.national.com.LIFESUPPORTPOLICY

NATIONAL’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTANDGENERALCOUNSELOFNATIONALSEMICONDUCTORCORPORATION.Asusedherein:

1.Lifesupportdevicesorsystemsaredevicesorsystemswhich,(a)areintendedforsurgicalimplantintothebody,or(b)supportorsustainlife,andwhosefailuretoperformwhenproperlyusedinaccordancewithinstructionsforuseprovidedinthelabeling,canbereasonablyexpectedtoresultinasignificantinjurytotheuser.BANNEDSUBSTANCECOMPLIANCE

NationalSemiconductormanufacturesproductsandusespackingmaterialsthatmeettheprovisionsoftheCustomerProductsStewardshipSpecification(CSP-9-111C2)andtheBannedSubstancesandMaterialsofInterestSpecification(CSP-9-111S2)andcontainno‘‘BannedSubstances’’asdefinedinCSP-9-111S2.

NationalSemiconductorAmericasCustomerSupportCenter

Email:new.feedback@nsc.comTel:1-800-272-9959

www.national.com

NationalSemiconductor

EuropeCustomerSupportCenter

Fax:+49(0)180-5308586Email:europe.support@nsc.com

DeutschTel:+49(0)6995086208EnglishTel:+44(0)8702402171FrançaisTel:+33(0)141918790

NationalSemiconductorAsiaPacificCustomerSupportCenter

Email:ap.support@nsc.com

NationalSemiconductor

JapanCustomerSupportCenterFax:81-3-5639-7507

Email:jpn.feedback@nsc.comTel:81-3-5639-7560

2.Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailureofthelifesupportdeviceorsystem,ortoaffectitssafetyoreffectiveness.