Features
•Single 1.65V - 1.95V Supply
•Serial Peripheral Interface (SPI) Compatible–Supports SPI Modes 0 and 3•66 MHz Maximum Clock Frequency•
Flexible, Uniform Erase Architecture–4-Kbyte Blocks–32-Kbyte Blocks–64-Kbyte Blocks–Full Chip Erase
•Individual Sector Protection with Global Protect/Unprotect Feature–Sixteen 64-Kbyte Physical Sectors
•Hardware Controlled Locking of Protected Sectors•Flexible Programming
–Byte/Page Program (1 to 256 Bytes)
•Automatic Checking and Reporting of Erase/Program Failures•JEDEC Standard Manufacturer and Device ID Read Methodology•
Low Power Dissipation
–7 mA Active Read Current (Typical)
–8 µA Deep Power-Down Current (Typical)•Endurance: 100,000 Program/Erase Cycles•Data Retention: 20 Years
•Complies with Full Industrial Temperature Range
•
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options–8-lead SOIC (150-mil wide)
–8-contact Ultra Thin DFN (5 mm x 6 mm x 0.6 mm)–11-ball dBGA (WLCSP)
1.Description
The AT25DF081 is a serial interface Flash memory device designed for use in a widevariety of high-volume consumer based applications in which program code is shad-owed from Flash memory into embedded or external RAM for execution. The flexibleerase architecture of the AT25DF081, with its erase granularity as small as 4-Kbytes,makes it ideal for data storage as well, eliminating the need for additional data storageEEPROM devices.
The physical sectoring and the erase block sizes of the AT25DF081 have been opti-mized to meet the needs of today's code and data storage applications. By optimizingthe size of the physical sectors and erase blocks, the memory space can be usedmuch more efficiently. Because certain code modules and data storage segmentsmust reside by themselves in their own protected sectors, the wasted and unusedmemory space that occurs with large sectored and large block erase Flash memorydevices can be greatly reduced. This increased memory space efficiency allows addi-tional code routines and data storage segments to be added while still maintaining thesame overall device density.
8-megabit1.65-volt Minimum SPI SerialFlash MemoryAT25DF081 3674E–DFLASH–8/08元器件交易网www.cecb2b.com
The AT25DF081 also offers a sophisticated method for protecting individual sectors againsterroneous or malicious program and erase operations. By providing the ability to individually pro-tect and unprotect sectors, a system can unprotect a specific sector to modify its contents whilekeeping the remaining sectors of the memory array securely protected. This is useful in applica-tions where program code is patched or updated on a subroutine or module basis, or inapplications where data storage segments need to be modified without running the risk of errantmodifications to the program code segments. In addition to individual sector protection capabili-ties, the AT25DF081 incorporates Global Protect and Global Unprotect features that allow theentire memory array to be either protected or unprotected all at once. This reduces overheadduring the manufacturing process since sectors do not have to be unprotected one-by-one priorto initial programming.
Specifically designed for use in 1.8-volt systems, the AT25DF081 supports read, program, anderase operations with a supply voltage range of 1.65V to 1.95V. No separate voltage is requiredfor programming and erasing.
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AT25DF081
2.Pin Descriptions and Pinouts
Table 2-1.
Symbol
Pin Descriptions
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin.The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.Operations at invalid VCC voltages may produce spurious results and should not be attempted.GROUND: The ground reference for the power supply. GND should be connected to the system ground.
AssertedState
Type
CSLowInput
SCKInput
SIInput
SOOutput
WPLowInput
HOLDLowInput
VCCGND
PowerPower
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Figure 2-1.
CS SO WP GND 1 2 3 4 8-SOIC Top View
8 7 6 5 VCCHOLDSCKSIFigure 2-2.
CS SO WP GND 1 2 3 4 8-UDFN Top View
VCC 7 HOLD 6 SCK 5 SI 8 Figure 2-3.
11-dBGA (Top View Through Back of Die)
1A BVCCCSCHOLDSODSCKWPESIGNDFNC NC NC2343.Block Diagram
CSCONTROL ANDPROTECTION LOGICI/O BUFFERSAND LATCHESSCKSISOSRAMDATA BUFFERINTERFACECONTROLANDLOGICADDRESS LATCHY-DECODERY-GATINGWPHOLDX-DECODERFLASHMEMORYARRAY4.Memory Array
To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev-els of granularity including a full chip erase. In addition, the array has been divided into physicalsectors of uniform size, of which each sector can be individually protected from program anderase operations. The size of the physical sectors is optimized for both code and data storageapplications, allowing both code and data segments to reside in their own isolatedregions.Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-down of each physical sector.
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Figure 4-1.
Memory Architecture Diagram
Block Erase DetailInternal Sectoring for64KB32KB4KBSector ProtectionBlock EraseBlock EraseBlock EraseBlock AddressFunction(D8h Command)(52h Command)(20h Command)Range4KB0FFFFFh–0FF000h4KB0FEFFFh–0FE000h4KB0FDFFFh–0FD000h32KB4KB0FCFFFh–0FC000h4KB0FBFFFh–0FB000h4KB0FAFFFh–0FA000h4KB0F9FFFh–0F9000h64KB 4KB0F8FFFh–0F8000h(Sector 15)64KB4KB0F7FFFh–0F7000h4KB0F6FFFh–0F6000h4KB0F5FFFh–0F5000h32KB4KB0F4FFFh–0F4000h4KB0F3FFFh–0F3000h4KB0F2FFFh–0F2000h4KB0F1FFFh–0F1000h4KB0F0FFFh–0F0000h4KB0EFFFFh–0EF000h4KB0EEFFFh–0EE000h4KB0EDFFFh–0ED000h32KB4KB0ECFFFh–0EC000h4KB0EBFFFh–0EB000h4KB0EAFFFh–0EA000h4KB0E9FFFh–0E9000h64KB 4KB0E8FFFh–0E8000h(Sector 14)64KB4KB0E7FFFh–0E7000h4KB0E6FFFh–0E6000h4KB0E5FFFh–0E5000h32KB4KB0E4FFFh–0E4000h4KB0E3FFFh–0E3000h4KB0E2FFFh–0E2000h4KB0E1FFFh–0E1000h4KB0E0FFFh–0E0000h•••• •••• ••••4KB00FFFFh–00F000h4KB00EFFFh–00E000h4KB00DFFFh–00D000h32KB4KB00CFFFh–00C000h4KB00BFFFh–00B000h4KB00AFFFh–00A000h4KB009FFFh–009000h64KB 4KB008FFFh–008000h(Sector 0)64KB4KB007FFFh–007000h4KB006FFFh–006000h4KB005FFFh–005000h32KB4KB004FFFh–004000h4KB003FFFh–003000h4KB002FFFh–002000h4KB001FFFh–001000h4KB000FFFh–000000h3674E–DFLASH–8/08
AT25DF081
Page Program Detail1-256 BytePage ProgramPage Address(02h Command)Range256 Bytes0FFFFFh–0FFF00h256 Bytes0FFEFFh–0FFE00h256 Bytes0FFDFFh–0FFD00h256 Bytes0FFCFFh–0FFC00h256 Bytes0FFBFFh–0FFB00h256 Bytes0FFAFFh–0FFA00h256 Bytes0FF9FFh–0FF900h256 Bytes0FF8FFh–0FF800h256 Bytes0FF7FFh–0FF700h256 Bytes0FF6FFh–0FF600h256 Bytes0FF5FFh–0FF500h256 Bytes0FF4FFh–0FF400h256 Bytes0FF3FFh–0FF300h256 Bytes0FF2FFh–0FF200h256 Bytes0FF1FFh–0FF100h256 Bytes0FF0FFh–0FF000h256 Bytes0FEFFFh–0FEF00h256 Bytes0FEEFFh–0FEE00h256 Bytes0FEDFFh–0FED00h256 Bytes0FECFFh–0FEC00h256 Bytes0FEBFFh–0FEB00h256 Bytes0FEAFFh–0FEA00h256 Bytes0FE9FFh–0FE900h256 Bytes0FE8FFh–0FE800h• • •256 Bytes0017FFh–001700h256 Bytes0016FFh–001600h256 Bytes0015FFh–001500h256 Bytes0014FFh–001400h256 Bytes0013FFh–001300h256 Bytes0012FFh–001200h256 Bytes0011FFh–001100h256 Bytes0010FFh–001000h256 Bytes000FFFh–000F00h256 Bytes000EFFh–000E00h256 Bytes000DFFh–000D00h256 Bytes000CFFh–000C00h256 Bytes000BFFh–000B00h256 Bytes000AFFh–000A00h256 Bytes0009FFh–000900h256 Bytes0008FFh–000800h256 Bytes0007FFh–000700h256 Bytes0006FFh–000600h256 Bytes0005FFh–000500h256 Bytes0004FFh–000400h256 Bytes0003FFh–000300h256 Bytes0002FFh–000200h256 Bytes0001FFh–000100h256 Bytes0000FFh–000000h5
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5.Device Operation
The AT25DF081 is controlled by a set of instructions that are sent from a host controller, com-monly referred to as the SPI Master. The SPI Master communicates with the AT25DF081 via theSPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), SerialInput (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each modediffering in respect to the SCK polarity and phase and how the polarity and phase control theflow of data on the SPI bus. The AT25DF081 supports the two most common modes, SPIModes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signalwhen in the inactive state (when the SPI Master is in standby mode and not transferring anydata). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and alwaysoutput on the falling edge of SCK.Figure 5-1.
CSSPI Mode 0 and 3
SCKSIMSBLSBSOMSBLSB6.Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CSpin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.Following the opcode, instruction dependent information such as address and data bytes wouldthen be clocked out by the SPI Master. All opcode, address, and data bytes are transferred withthe most significant bit (MSB) first. An operation is ended by deasserting the CS pin.Opcodes not supported by the AT25DF081 will be ignored by the device and no operation will bestarted. The device will continue to ignore any data presented on the SI pin until the start of thenext operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-serted before complete opcode and address information is sent to the device, then no operationwill be performed and the device will simply return to the idle state and wait for the nextoperation.
Addressing of the device requires a total of three bytes of information to be sent, representingaddress bits A23-A0. Since the upper address limit of the AT25DF081 memory array is0FFFFFh, address bits A23-A20 are always ignored by the device.
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AT25DF081
Table 6-1.
CommandRead Commands
Read Array
Read Array (Low Frequency)Program and Erase Commands
Block Erase (4-KBytes)Block Erase (32-KBytes)Block Erase (64-KBytes)Chip Erase
Byte/Page Program (1 to 256 Bytes)Protection Commands
Write EnableWrite DisableProtect SectorUnprotect SectorGlobal Protect/UnprotectRead Sector Protection RegistersStatus Register Commands
Read Status RegisterWrite Status RegisterMiscellaneous Commands
Read Manufacturer and Device IDDeep Power-Down
Resume from Deep Power-Down
9FhB9hABh
1001 11111011 10011010 1011
000
000
1 to 400
05h01h
0000 01010000 0001
00
00
1+1
3Ch06h04h36h39h
0000 01100000 01000011 01100011 1001
0033
0000
0000
20h52hD8h60hC7h02h
0010 00000101 00101101 10000110 00001100 01110000 0010
333003
000000
000001+
0Bh03h
0000 10110000 0011
33
10
1+1+
Command Listing
Opcode
Address Bytes
Dummy Bytes
Data Bytes
Use Write Status Register command
0011 1100
3
0
1+
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7.Read Commands
7.1
Read Array
The Read Array command can be used to sequentially read a continuous stream of data fromthe device by simply providing the SCK signal once the initial starting address has been speci-fied. The device incorporates an internal address counter that automatically increments on everyclock cycle.
Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcodedepends on the maximum SCK frequency that will be used to read data from the device. The0Bh opcode can be used at any SCK frequency up to the maximum specified by fSCK. The 03hopcode can be used for lower frequency read operations up to the maximum specified by fRDLF.To perform the Read Array operation, the CS pin must first be asserted and the appropriateopcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, thethree address bytes must be clocked in to specify the starting address location of the first byte toread within the memory array. If the 0Bh opcode is used, then one don’t care byte must also beclocked in after the three address bytes.
After the three address bytes (and the one don’t care byte if using opcode 0Bh) have beenclocked in, additional clock cycles will result in serial data being output on the SO pin. The datais always output with the MSB of a byte first. When the last byte (0FFFFFh) of the memory arrayhas been read, the device will continue reading back at the beginning of the array (000000h). Nodelays will be incurred when wrapping around from the end of the array to the beginning of thearray.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-ance state. The CS pin can be deasserted at any time and does not require that a full byte ofdata be read.
Figure 7-1.
Read Array – 0Bh Opcode
CS01234567891011122930313233343536373839404142434445464748SCKOPCODEADDRESS BITS A23-A0011AMSBDON'T CAREAAXMSBSI0MSB0001AAAAAAXXXXXXXDATA BYTE 1SOHIGH-IMPEDANCEDMSBDDDDDDDDMSBDFigure 7-2.Read Array – 03h Opcode
CS0123456789101112293031323334353637383940SCKOPCODEADDRESS BITS A23-A0011AMSBSI0MSB0000AAAAAAAADATA BYTE 1SOHIGH-IMPEDANCEDMSBDDDDDDDDMSBD8
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AT25DF081
8.Program and Erase Commands
8.1
Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes ofdata to be programmed into previously erased memory locations. An erased memory location isone that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/PageProgram command can be started, the Write Enable command must have been previouslyissued to the device (see Write Enable command description) to set the Write Enable Latch(WEL) bit of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the devicefollowed by the three address bytes denoting the first byte location of the memory array to beginprogramming at. After the address bytes have been clocked in, data can then be clocked into thedevice and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte pageboundary (A7-A0 are not all 0), then special circumstances regarding which memory locationswill be programmed will apply. In this situation, any data that is sent to the device that goesbeyond the end of the page will wrap around back to the beginning of the same page. For exam-ple, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent tothe device, then the first two bytes of data will be programmed at addresses 0000FEh and0000FFh while the last byte of data will be programmed at address 000000h. The remainingbytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change.In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytessent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro-gram it into the appropriate memory array locations based on the starting address specified byA23-A0 and the number of complete data bytes sent to the device. If less than 256 bytes of datawere sent to the device, then the remaining bytes within the page will not be altered. The pro-gramming of the data bytes is internally self-timed and should take place in a time of tPP.The three address bytes and at least one complete byte of data must be clocked into the devicebefore the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries(multiples of eight bits); otherwise, the device will abort the operation and no data will be pro-grammed into the memory array. In addition, if the address specified by A23-A0 points to amemory location within a sector that is in the protected state (see “Protect Sector” on page 13),then the Byte/Page Program command will not be executed, and the device will return to the idlestate once the CS pin has been deasserted. The WEL bit in the Status Register will be resetback to the logical “0” state if the program cycle aborts due to an incomplete address being sent,an incomplete byte of data being sent, or because the memory location to be programmed isprotected.
While the device is programming, the Status Register can be read and will indicate that thedevice is busy. For faster throughput, it is recommended that the Status Register be polledrather than waiting the tPP time to determine if the data bytes have finished programming. Atsome point before the program cycle completes, the WEL bit in the Status Register will be resetback to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a bytelocation fails to program properly. If a programming error arises, it will be indicated by the EPEbit in the Status Register.
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Figure 8-1.Byte Program
CS01234567891011122930313233343536373839SCKOPCODEADDRESS BITS A23-A0010AMSBDATA INAADMSBSI0MSB0000AAAAAADDDDDDDSOFigure 8-2.
Page Program
HIGH-IMPEDANCECS01234567892930313233343536373839SCKOPCODEADDRESS BITS A23-A0010AMSBDATA IN BYTE 1DMSBDATA IN BYTE nDDMSBSI0MSB0000AAAAADDDDDDDDDDDDDSOHIGH-IMPEDANCE8.2Block Erase
A block of 4K-, 32K-, or 64K-bytes can be erased (all bits set to the logical “1” state) in a singleoperation by using one of three different opcodes for the Block Erase command. An opcode of20h is used for a 4K-byte erase, an opcode of 52h is used for a 32K-byte erase, and an opcodeof D8h is used for a 64K-byte erase. Before a Block Erase command can be started, the WriteEnable command must have been previously issued to the device to set the WEL bit of the Sta-tus Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the threeaddress bytes specifying an address within the 4K-, 32K-, or 64K-byte block to be erased mustbe clocked in. Any additional data clocked into the device will be ignored. When the CS pin isdeasserted, the device will erase the appropriate block. The erasing of the block is internallyself-timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do notneed to be decoded by the device. Therefore, for a 4K-byte erase, address bits A11-A0 will beignored by the device and their values can be either a logical “1” or “0”. For a 32K-byte erase,address bits A14-A0 will be ignored, and for a 64K-byte erase, address bits A15-A0 will beignored by the device. Despite the lower order address bits not being decoded by the device, thecomplete three address bytes must still be clocked into the device before the CS pin is deas-serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);otherwise, the device will abort the operation and no erase operation will be performed.
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AT25DF081
If the address specified by A23-A0 points to a memory location within a sector that is in the pro-tected state, then the Block Erase command will not be executed, and the device will return tothe idle state once the CS pin has been deasserted.The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycleaborts due to an incomplete address being sent or because a memory location within the regionto be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and willindicate that the device is busy. For faster throughput, it is recommended that the Status Regis-ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. Atsome point before the erase cycle completes, the WEL bit in the Status Register will be resetback to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte loca-tion fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in theStatus Register.Figure 8-3.
Block Erase
CS0123456789101112262728293031SCKOPCODEADDRESS BITS A23-A0CCAMSBSICMSBCCCCCAAAAAAAAAAASOHIGH-IMPEDANCE8.3Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command.Before a Chip Erase command can be started, the Write Enable command must have been pre-viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference indevice functionality when utilizing the two opcodes, so they can be used interchangeably. Toperform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.Since the entire memory array is to be erased, no address bytes need to be clocked into thedevice, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted,the device will erase the entire memory array. The erasing of the device is internally self-timedand should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and theCS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, noerase will be performed. In addition, if any sector of the memory array is in the protected state,then the Chip Erase command will not be executed, and the device will return to the idle stateonce the CS pin has been deasserted. The WEL bit in the Status Register will be reset back tothe logical “0” state if a sector is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and willindicate that the device is busy. For faster throughput, it is recommended that the Status Regis-11
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ter be polled rather than waiting the tCHPE time to determine if the device has finished erasing. Atsome point before the erase cycle completes, the WEL bit in the Status Register will be resetback to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte loca-tion fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in theStatus Register.Figure 8-4.
Chip Erase
CS01234567SCKOPCODESICMSBCCCCCCCSOHIGH-IMPEDANCE9.Protection Commands and Features
9.1
Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis-ter to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector,Unprotect Sector, or Write Status Register command can be executed. This makes the issuanceof these commands a two step process, thereby reducing the chances of a command beingaccidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to theissuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06hmust be clocked into the device. No address bytes need to be clocked into the device, and anydata clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit inthe Status Register will be set to a logical “1”. The complete opcode must be clocked into thedevice before the CS pin is deasserted, and the CS pin must be deasserted on an even byteboundary (multiples of eight bits); otherwise, the device will abort the operation and the state ofthe WEL bit will not change.Figure 9-1.
Write Enable
CS01234567SCKOPCODESI0MSB0000110SO12
HIGH-IMPEDANCEAT25DF081
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AT25DF081
9.2
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-ister to the logical “0” state. With the WEL bit reset, all program, erase, Protect Sector, UnprotectSector, and Write Status Register commands will not be executed. The Write Disable commandis also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bitto be reset; for more details, refer to the WEL bit section of the Status Register description onpage 21.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04hmust be clocked into the device. No address bytes need to be clocked into the device, and anydata clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit inthe Status Register will be reset to a logical “0”. The complete opcode must be clocked into thedevice before the CS pin is deasserted, and the CS pin must be deasserted on an even byteboundary (multiples of eight bits); otherwise, the device will abort the operation and the state ofthe WEL bit will not change.Figure 9-2.
Write Disable
CS01234567SCKOPCODESI0MSB0000100SOHIGH-IMPEDANCE9.3Protect Sector
Every physical sector of the device has a corresponding single-bit Sector Protection Registerthat is used to control the software protection of a sector. Upon device power-up or after adevice reset, each Sector Protection Register will default to the logical “1” state indicating that allsectors are protected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the correspondingSector Protection Register to the logical “1” state. The following table outlines the two states ofthe Sector Protection Registers.Table 9-1.
Value01
Sector Protection Register Values
Sector Protection Status
Sector is unprotected and can be programmed and erased.
Sector is protected and cannot be programmed or erased. This is the default state.
Before the Protect Sector command can be issued, the Write Enable command must have beenpreviously issued to set the WEL bit in the Status Register to a logical “1”. To issue the ProtectSector command, the CS pin must first be asserted and the opcode of 36h must be clocked intothe device followed by three address bytes designating any address within the sector to belocked. Any additional data clocked into the device will be ignored. When the CS pin is deas-serted, the Sector Protection Register corresponding to the physical sector addressed by A23-13
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A0 will be set to the logical “1” state, and the sector itself will then be protected from programand erase operations. In addition, the WEL bit in the Status Register will be reset back to the log-ical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deas-serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);otherwise, the device will abort the operation, the state of the Sector Protection Register will beunchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the SectorProtection Registers can themselves be locked from updates by using the SPRL (Sector Protec-tion Registers Locked) bit of the Status Register (please refer to “Status Register Commands”on page 20 for more details). If the Sector Protection Registers are locked, then any attempts toissue the Protect Sector command will be ignored, and the device will reset the WEL bit in theStatus Register back to a logical “0” and return to the idle state once the CS pin has beendeasserted.Figure 9-3.
Protect Sector
CS0123456789101112262728293031SCKOPCODEADDRESS BITS A23-A0110AMSBSI0MSB0110AAAAAAAAAAASOHIGH-IMPEDANCE9.4Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the correspond-ing Sector Protection Register to the logical “0” state (see Table 9-1 on page 13 for SectorProtection Register values). Every physical sector of the device has a corresponding single-bitSector Protection Register that is used to control the software protection of a sector.
Before the Unprotect Sector command can be issued, the Write Enable command must havebeen previously issued to set the WEL bit in the Status Register to a logical “1”. To issue theUnprotect Sector command, the CS pin must first be asserted and the opcode of 39h must beclocked into the device. After the opcode has been clocked in, the three address bytes designat-ing any address within the sector to be unlocked must be clocked in. Any additional data clockedinto the device after the address bytes will be ignored. When the CS pin is deasserted, the Sec-tor Protection Register corresponding to the sector addressed by A23-A0 will be reset to thelogical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the StatusRegister will be reset back to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deas-serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);otherwise, the device will abort the operation, the state of the Sector Protection Register will beunchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
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As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Pro-tection Registers can themselves be locked from updates by using the SPRL (Sector ProtectionRegisters Locked) bit of the Status Register (please refer to “Status Register Commands” onpage 20 for more details). If the Sector Protection Registers are locked, then any attempts toissue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in theStatus Register back to a logical “0” and return to the idle state once the CS pin has beendeasserted.Figure 9-4.
Unprotect Sector
CS0123456789101112262728293031SCKOPCODEADDRESS BITS A23-A0001AMSBSI0MSB0111AAAAAAAAAAASOHIGH-IMPEDANCE9.5Global Protect/Unprotect
The Global Protect and Global Unprotect features can work in conjunction with the Protect Sec-tor and Unprotect Sector functions. For example, a system can globally protect the entirememory array and then use the Unprotect Sector command to individually unprotect certain sec-tors and individually reprotect them later by using the Protect Sector command. Likewise, asystem can globally unprotect the entire memory array and then individually protect certain sec-tors as needed.
Performing a Global Protect or Global Unprotect is accomplished by writing a certain combina-tion of data to the Status Register using the Write Status Register command (see “Write StatusRegister” section on page 22 for command execution details). The Write Status Register com-mand is also used to modify the SPRL (Sector Protection Registers Locked) bit to controlhardware and software locking.
To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met and thesystem must write a logical “1” to bits 5, 4, 3, and 2 of the Status Register. Conversely, to per-form a Global Unprotect, the same WP and SPRL conditions must be met but the system mustwrite a logical “0” to bits 5, 4, 3, and 2 of the Status Register. Table 9-2 details the conditionsnecessary for a Global Protect or Global Unprotect to be performed.
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Table 9-2.Valid SPRL and Global Protect/Unprotect Conditions
NewWrite StatusRegister DataBit
7 6 5 4 3 2 1 00 x 0 0 0 0 x x0 x 0 0 0 1 x x
↕
0 x 1 1 1 0 x x0 x 1 1 1 1 x x
Protection Operation
Global Unprotect – all Sector Protection Registers reset to 0No change to current protection.No change to current protection.No change to current protection.
Global Protect – all Sector Protection Registers set to 1Global Unprotect – all Sector Protection Registers reset to 0No change to current protection.No change to current protection.No change to current protection.
Global Protect – all Sector Protection Registers set to 1
WPState
CurrentSPRLValueNewSPRLValue0000011111
00
1 x 0 0 0 0 x x1 x 0 0 0 1 x x
↕
1 x 1 1 1 0 x x1 x 1 1 1 1 x x
No change to the current protection level. All sectors currently
protected will remain protected and all sectors currently unprotected will remain unprotected.
0
1
x x x x x x x x
The Sector Protection Registers are hard-locked and cannot be
changed when the WP pin is LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change SPRL back to a 0).
Global Unprotect – all Sector Protection Registers reset to 0No change to current protection.No change to current protection.No change to current protection.
Global Protect – all Sector Protection Registers set to 1Global Unprotect – all Sector Protection Registers reset to 0No change to current protection.No change to current protection.No change to current protection.
Global Protect – all Sector Protection Registers set to 1No change to the current protection level. All sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected.
The Sector Protection Registers are soft-locked and cannot be changed when the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. However, the
SPRL bit can be changed back to a 0 from a 1 since the WP pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from a 1 to a 0.
00000111110000011111
0 x 0 0 0 0 x x0 x 0 0 0 1 x x
↕
0 x 1 1 1 0 x x0 x 1 1 1 1 x x
1
0
1 x 0 0 0 0 x x1 x 0 0 0 1 x x
↕
1 x 1 1 1 0 x x1 x 1 1 1 1 x x0 x 0 0 0 0 x x0 x 0 0 0 1 x x
↕
0 x 1 1 1 0 x x0 x 1 1 1 1 x x
1
1
1 x 0 0 0 0 x x1 x 0 0 0 1 x x
↕
1 x 1 1 1 0 x x1 x 1 1 1 1 x x
Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector ProtectionRegisters are not locked), then writing a 00h to the Status Register will perform a Global Unpro-tect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the Status Register willperform a Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, ofcourse, be changed to a logical “1” by writing an FFh if software-locking or hardware-locking isdesired along with the Global Protect.
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If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-tect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit froma logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the system can write anF0h to change the SPRL bit from a logical “0” to a logical “1” without affecting the current sectorprotection status (no changes will be made to the Sector Protection Registers).
When writing to the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will bedecoded by the device for the purposes of the Global Protect and Global Unprotect functions.Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the Status Register,bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status ofthe WP pin and the sector protection status. Please refer to the “Read Status Register” sectionand Table 10-1 on page 20 for details on the Status Register format and what values can beread for bits 5, 4, 3, and 2.
9.6Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection statusof each sector. Reading the Sector Protection Registers, however, will not determine the statusof the WP pin.To read the Sector Protection Register for a particular sector, the CS pin must first be assertedand the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three addressbytes designating any address within the sector must be clocked in. After the last address bytehas been clocked in, the device will begin outputting data on the SO pin during every subse-quent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denotethe value of the appropriate Sector Protection RegisterTable 9-3.
00hFFh
Read Sector Protection Register – Output Data
Sector Protection Register Value
Sector Protection Register value is 0 (sector is unprotected).Sector Protection Register value is 1 (sector is protected).
Output Data
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-ance state. The CS pin can be deasserted at any time and does not require that a full byte ofdata be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status(SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors aresoftware protected (please refer to “Status Register Commands” on page 20 for more details).
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Figure 9-5.Read Sector Protection Register
CS0123456789101112293031323334353637383940SCKOPCODEADDRESS BITS A23-A0100AMSBSI0MSB0111AAAAAAAADATA BYTESOHIGH-IMPEDANCEDMSBDDDDDDDDMSBD9.7Protected States and the Write Protect (WP) PinThe WP pin is not linked to the memory array itself and has no direct effect on the protection sta-tus of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector ProtectionRegisters Locked) bit in the Status Register, is used to control the hardware locking mechanismof the device. For hardware locking to be active, two conditions must be met – the WP pin mustbe asserted and the SPRL bit must be in the logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bititself is also locked. Therefore, sectors that are protected will be locked in the protected state,and sectors that are unprotected will be locked in the unprotected state. These states cannot bechanged as long as hardware locking is active, so the Protect Sector, Unprotect Sector, andWrite Status Register commands will be ignored. In order to modify the protection status of asector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must bereset back to the logical “0” state using the Write Status Register command. When resetting theSPRL bit back to a logical “0”, it is not possible to perform a Global Protect or Global Unprotectat the same time since the Sector Protection Registers remain soft-locked until after the WriteStatus Register command has been executed.
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”,the only way to reset the bit back to the logical “0” state is to power-cycle or reset the device.This allows a system to power-up with all sectors software protected but not hardware locked.Therefore, sectors can be unprotected and protected as needed and then hardware locked at alater time by simply setting the SPRL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bitin the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. Thisprovides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector com-mands from being processed. When changing the SPRL bit to a logical “1” from a logical “0”, it isalso possible to perform a Global Protect or Global Unprotect at the same time by writing theappropriate values into bits 5, 4, 3, and 2 of the Status Register.
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The tables below detail the various protection and locking states of the device.Table 9-4.
WPX
(Don't Care)Note:
Software Protection Register States
Sector Protection Register
n(1)
01
Sectorn(1)UnprotectedProtected
1.“n” represents a sector number
Table 9-5.
WPSPRL
Hardware and Software Locking
Locking
SPRL Change Allowed
Sector Protection RegistersUnlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed.Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed.Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed.Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed.
00Can be modified from 0 to 1
01
HardwareLocked
Locked
10Can be modified from 0 to 1
11
SoftwareLocked
Can be modified from 1 to 0
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10.Status Register Commands
10.1
Read Status Register
The Status Register can be read to determine the device’s ready/busy status, as well as the sta-tus of many other functions such as Hardware Locking and Software Protection. The StatusRegister can be read at any time, including during an internally self-timed program or eraseoperation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must beclocked into the device. After the last bit of the opcode has been clocked in, the device will beginoutputting Status Register data on the SO pin during every subsequent clock cycle. After the lastbit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself startingagain with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. Thedata in the Status Register is constantly being updated, so each repeating sequence will outputnew data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pininto a high-impedance state. The CS pin can be deasserted at any time and does not requirethat a full byte of data be read.
Table 10-1.
Bit(1)765
SPRLRESEPE
Status Register Format
Name
Sector Protection Registers LockedReserved for future useErase/Program Error
Type(2)R/WRR
Description010010100
Sector Protection Registers are unlocked (default).Sector Protection Registers are locked.Reserved for future use.
Erase or program operation was successful.Erase or program error detected.WP is asserted.WP is deasserted.All sectors are software unprotected (all Sector Protection Registers are 0).
Some sectors are software protected. Read individual Sector Protection Registers to determine which sectors are protected.Reserved for future use.
All sectors are software protected (all Sector Protection Registers are 1 – default).Device is not write enabled (default).Device is write enabled.Device is ready.
Device is busy with an internal operation.
4WPPWrite Protect (WP) Pin StatusR
3:2SWPSoftware Protection StatusR
011011
1WELWrite Enable Latch StatusR
0101
0Notes:
RDY/BSYReady/Busy StatusR
1.Only bit 7 of the Status Register will be modified when using the Write Status Register command.2.R/W = Readable and writeable
R = Readable only
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10.1.1
SPRL Bit
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not.When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and can-not be modified with the Protect Sector and Unprotect Sector commands (the device will ignorethese commands). In addition, the Global Protect and Global Unprotect features cannot be per-formed. Any sectors that are presently protected will remain protected, and any sectors that arepresently unprotected will remain unprotected.
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked andcan be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Pro-tect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to thelogical “0” state after a power-up or a device reset.
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pinis asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Regis-ters are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset theSPRL bit back to a logical “0” using the Write Status Register command, the WP pin will have tofirst be deasserted.
The SPRL bit is the only bit of the Status Register that can be user modified via the Write StatusRegister command.
10.1.2
WPP Bit
The WPP bit can be read to determine if the WP pin has been asserted or not.10.1.3
EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully ornot. If at least one byte during the erase or program operation did not erase or program properly,then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or pro-gram operation aborts for any reason such as an attempt to erase or program a protected regionor if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updatedafter every erase and program operation.
10.1.4
SWP Bits
The SWP bits provide feedback on the software protection status for the device. There are threepossible combinations of the SWP bits that indicate whether none, some, or all of the sectorshave been protected using the Protect Sector command or the Global Protect feature. If theSWP bits indicate that some of the sectors have been protected, then the individual Sector Pro-tection Registers can be read with the Read Sector Protection Registers command to determinewhich sectors are in fact protected.
10.1.5
WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit isin the logical “0” state, the device will not accept any program, erase, Protect Sector, UnprotectSector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after adevice power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati-cally under the following conditions:
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•Write Disable operation completes successfully
•Write Status Register operation completes successfully or aborts•Protect Sector operation completes successfully or aborts•Unprotect Sector operation completes successfully or aborts•Byte/Page Program operation completes successfully or aborts•Block Erase operation completes successfully or aborts•Chip Erase operation completes successfully or aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation abortsdue to an incomplete or unrecognized opcode being clocked into the device before the CS pin isdeasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entireopcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-mand must have been clocked into the device.
10.1.6
RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a programor erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erasecycle, new Status Register data must be continually clocked out of the device until the state ofthe RDY/BSY bit changes from a logical “1” to a logical “0”.Figure 10-1.Read Status Register
CS0123456789101112131415161718192021222324SCKOPCODESI0MSB0000101STATUS REGISTER DATASTATUS REGISTER DATADMSBSOHIGH-IMPEDANCEDMSBDDDDDDDDDDDDDDDMSBD10.2Write Status Register
The Write Status Register command is used to modify the SPRL bit of the Status Registerand/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-ter command can be issued, the Write Enable command must have been previously issued toset the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcodeof 01h must be clocked into the device followed by one byte of data. The one byte of data con-sists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect orUnprotect should be performed, and two additional don’t care bits (see Table 10-2). Any addi-tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, theSPRL bit in the Status Register will be modified and the WEL bit in the Status Register will bereset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit beforethe Write Status Register command was executed (the prior state of the SPRL bit) will determinewhether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “GlobalProtect/Unprotect” section on page 15 for more details.
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The complete one byte of data must be clocked into the device before the CS pin is deasserted,and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); other-wise, the device will abort the operation, the state of the SPRL bit will not change, no potentialGlobal Protect or Unprotect will be performed, and the WEL bit in the Status Register will bereset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is madeto reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Registercommand will be ignored, and the WEL bit in the Status Register will be reset back to the logical“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.Table 10-2.
Bit 7SPRL
Write Status Register Format
Bit 6X
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1X
Bit 0X
Global Protect/Unprotect
Figure 10-2.Write Status Register
CS0123456789101112131415SCKOPCODESTATUS REGISTER IN001DMSBSI0MSB0000XDDDDXXSOHIGH-IMPEDANCE11.Other Commands and Functions
11.1
Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically queryand identify the device while it is in system. The identification method and the command opcodecomply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPICompatible Serial Interface Memory Devices”. The type of information that can be read from thedevice includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-dor specific Extended Device Information.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fhmust be clocked into the device. After the opcode has been clocked in, the device will begin out-putting the identification data on the SO pin during the subsequent clock cycles. The first bytethat will be output will be the Manufacturer ID followed by two bytes of Device ID information.The fourth byte output will be the Extended Device Information String Length, which will be 00hindicating that no Extended Device Information follows. After the Extended Device InformationString Length byte is output, the SO pin will go into a high-impedance state; therefore, additionalclock cycles will have no affect on the SO pin and no data will be output. As indicated in theJEDEC standard, reading the Extended Device Information String Length and any subsequentdata is optional.
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Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and putthe SO pin into a high-impedance state. The CS pin can be deasserted at any time and does notrequire that a full byte of data be read.
Table 11-1.
1234
Manufacturer and Device ID Information
Data TypeManufacturer IDDevice ID (Part 1)Device ID (Part 2)
Extended Device Information String Length
Value1Fh45h02h00h
Byte No.
Table 11-2.
Data TypeManufacturer ID
Manufacturer and Device ID Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HexValue1Fh
DetailsJEDEC Code:Family Code:Density Code:Sub Code:
Product Version:
0001 1111 (1Fh for Atmel)010 (AT25DF/26DFxxx series)00101 (8-Mbit)000 (Standard series)00010
JEDEC Assigned Code
0
0Family Code0
1Sub Code0
0
0
0
0
0
0
0
1
1
1Density Code
1
0
1
1
1
Device ID (Part 1)47h
Device ID (Part 2)
Product Version Code0
0
1
0
00h
Figure 11-1.Read Manufacturer and Device ID
CS067814151622232430313238SCKOPCODESI9FhSOHIGH-IMPEDANCE1FhMANUFACTURER ID45hDEVICE IDBYTE 102hDEVICE IDBYTE 200hEXTENDEDDEVICEINFORMATIONSTRING LENGTHNote: Each transitionshown for SI and SO represents one byte (8 bits)24
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11.2
Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less poweras long as the CS pin remains deasserted and no internal operation is in progress. The DeepPower-Down command offers the ability to place the device into an even lower power consump-tion state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read StatusRegister command will be ignored with the exception of the Resume from Deep Power-Downcommand. Since all commands will be ignored, the mode can be used as an extra protectionmechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clockingin the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into thedevice after the opcode will be ignored. When the CS pin is deasserted, the device will enter theDeep Power-Down mode within the maximum time of tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin mustbe deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abortthe operation and return to the standby mode once the CS pin is deasserted. In addition, thedevice will default to the standby mode after a power-cycle or a device reset.
The Deep Power-Down command will be ignored if an internally self-timed operation such as aprogram or erase cycle is in progress. The Deep Power-Down command must be reissued afterthe internally self-timed operation has been completed in order for the device to enter the DeepPower-Down mode.
Figure 11-2.Deep Power-Down
CS01234567tEDPDSCKOPCODESI1MSB0111001SOHIGH-IMPEDANCEActive CurrentICCStandby Mode CurrentDeep Power-Down Mode Current25
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11.3Resume from Deep Power-Down
In order exit the Deep Power-Down mode and resume normal device operation, the Resumefrom Deep Power-Down command must be issued. The Resume from Deep Power-Down com-mand is the only command that the device will recognize while in the Deep Power-Down mode.To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode ofABh must be clocked into the device. Any additional data clocked into the device after theopcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to the standby mode. After the devicehas returned to the standby mode, normal command operations such as Read Array can beresumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is notdeasserted on an even byte boundary (multiples of eight bits), then the device will abort theoperation and return to the Deep Power-Down mode.Figure 11-3.Resume from Deep Power-Down
CS01234567tRDPDSCKOPCODESI1MSB0101011SOHIGH-IMPEDANCEActive CurrentICCDeep Power-Down Mode CurrentStandby Mode Current26
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11.4
Hold
The HOLD pin is used to pause the serial communication with the device without having to stopor reset the clock sequence. The Hold mode, however, does not have an affect on any internallyself-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in prog-ress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue untilit is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activatedsimply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted duringthe SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK lowpulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin areasserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pinand the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted whilein the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deassertedduring the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then theHold mode won't end until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that mayhave been started will be aborted, and the device will reset the WEL bit in the Status Registerback to the logical “0” state.
Figure 11-4.Hold Mode
CSSCKHOLDHoldHoldHold27
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12.Electrical Specifications
12.1
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature Under Bias...............................-55°C to +125°CStorage Temperature....................................-65°C to +150°CAll Input Voltages(including NC Pins)
with Respect to Ground.....................................-0.6V to +3.8VAll Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.5V
12.2DC and AC Operating Range
AT25DF081
Ind.
-40°C to +85°C1.65V to 1.95V
Operating Temperature (Case)VCC Power Supply
12.3DC Characteristics
ParameterStandby Current
Deep Power-Down Current
Condition
CS, WP, HOLD = VCC,all inputs at CMOS levelsCS, WP, HOLD = VCC,all inputs at CMOS levelsf = 66 MHz, IOUT = 0 mA,CS = VIL, VCC = Maxf = 50 MHz; IOUT = 0 mA,CS = VIL, VCC = Maxf = 33 MHz, IOUT = 0 mA,CS = VIL, VCC = Maxf = 20 MHz, IOUT = 0 mA,CS = VIL, VCC = Max
Min
Typ25898761214
Max35141211
mA
1091517110.2 x VCC
0.8 x VCC
IOL = 100 µA, VCC = MinIOH = -100 µA, VCC = Min
VCC - 0.2
0.2
mAmAµAµAVVVVUnitsµAµA
SymbolISBIDPD
ICC1
Active Current, Read Operation
ICC2ICC3ILIILOVILVIHVOLVOH
Active Current, Program OperationActive Current, Erase OperationInput Leakage CurrentOutput Leakage CurrentInput Low VoltageInput High VoltageOutput Low VoltageOutput High Voltage
CS = VCC, VCC = Max
CS = VCC, VCC = Max
VIN = CMOS levelsVOUT = CMOS levels
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12.4
fSCKfRDLFtSCKHtSCKLtSCKR(1)tSCKF(1)tCSHtCSLStCSLHtCSHStCSHHtDStDHtDIS(1)tV(2)tOHtHLStHLHtHHtHHHtHLQZ(1)tHHQX(1)tWPS(1)(3)tWPH(1)(3)tSECP(1)tSECUP(1)tEDPD(1)tRDPD(1)Notes:
AC Characteristics
Parameter
Serial Clock (SCK) Frequency
SCK Frequency for Read Array (Low Frequency – 03h opcode)SCK High TimeSCK Low Time
SCK Rise Time, Peak-to-Peak (Slew Rate)SCK Fall Time, Peak-to-Peak (Slew Rate)Chip Select High Time
Chip Select Low Setup Time (relative to SCK)Chip Select Low Hold Time (relative to SCK)Chip Select High Setup Time (relative to SCK)Chip Select High Hold Time (relative to SCK)Data In Setup TimeData In Hold TimeOutput Disable TimeOutput Valid TimeOutput Hold Time
HOLD Low Setup Time (relative to SCK)HOLD Low Hold Time (relative to SCK)HOLD High Setup Time (relative to SCK)HOLD High Hold Time (relative to SCK)HOLD Low to Output High-ZHOLD High to Output Low-ZWrite Protect Setup TimeWrite Protect Hold Time
Sector Protect Time (from Chip Select High)Sector Unprotect Time (from Chip Select High)Chip Select High to Deep Power-DownChip Select High to Standby Mode
1.Not 100% tested (value guaranteed by design and characterization).2.15 pF load at 66 MHz, 30 pF load at 60 MHz.
3.Only applicable as a constraint for the Write Status Register command when SPRL = 1.
20100
2020335
05555
77
nsnsnsnsµsµs
6.86.80.10.150555523
77
Min
Max6633
UnitsMHzMHznsnsV/nsV/nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
Symbol
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12.5
tPPtBP
Program and Erase Characteristics
Parameter
Page Program Time (256 Bytes)Byte Program Time
4-Kbyte
Min
Typ1.015503506008
20060095014200
secnsms
Max5.0
Unitsmsµs
Symbol
tBLKEtCHPE(1)tWRSR(1)Notes:
Block Erase Time32-Kbyte64-Kbyte
Chip Erase Time
Write Status Register Time
1.Not 100% tested (value guaranteed by design and characterization).
12.6
tVCSLtPUWVPOR
Power-Up Conditions
Parameter
Minimum VCC to Chip Select Low Time
Power-up Device Delay Before Program or Erase AllowedPower-On Reset Voltage
0.9Min70
101.1Max
UnitsµsmsV
Symbol
12.7Input Test Waveforms and Measurement Levels
0.9VCCAC DRIVING LEVELS 0.1VCCtR, tF < 2 ns (10% to 90%) AC MEASUREMENTLEVEL VCC/212.8Output Test Load
DEVICEUNDERTEST30 pF30
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AT25DF081
13.AC Waveforms
Figure 13-1.Serial Input Timing
tCSHCStCSLStCSLHtCSHHtSCKHtSCKLtCSHSSCKtDStDHSIMSBLSBMSBSOHIGH-IMPEDANCEFigure 13-2.Serial Output Timing
CStSCKHtSCKLtDISSCKSItOHtVtVSOFigure 13-3.HOLD Timing – Serial InputCSSCKtHHHtHLStHLHtHHSHOLDSISOHIGH-IMPEDANCE3674E–DFLASH–8/08
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Figure 13-4.HOLD Timing – Serial OutputCSSCKtHHHtHLStHLHtHHSHOLDSItHLQZtHHQXSOFigure 13-5.WP Timing for Write Status Register Command When SPRL = 1CStWPStWPHWPSCKSI0MSB OFWRITE STATUS REGISTEROPCODE00XLSB OFWRITE STATUS REGISTERDATA BYTEMSBMSB OFNEXT OPCODESOHIGH-IMPEDANCE32
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14.Ordering Information
14.1
Ordering Code Detail – Standard Package Offerings
AT25DF081–SSHN–BAtmel DesignatorShipping Carrier OptionB = Bulk (tubes)Y = TraysT = Tape and reelProduct FamilyOperating VoltageN = 1.65V minimum (1.65V to 1.95V) Device Density08 = 8-megabitDevice GradeH = Green, NiPdAu lead finish, industrial temperature range (–40°C to +85°C)U = Green, Matte Sn or Sn alloy, industrial temperature range (–40°C to +85°C)Interface1 = SerialPackage OptionSS = 8-lead, 0.150\" wide SOICM = 8-contact, 5mm x 6mm UDFNU = 11-ball dBGA (WLCSP)14.2Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code
Package8S1
NiPdAu
8MA111U1(2)
SnAgCu
1.65V to 1.95V
66
Industrial(-40°C to +85°C)
Lead Finish
Operating Voltage
fSCK (MHz)
Operation Range
AT25DF081-SSHN-BAT25DF081-SSHN-TAT25DF081-MHN-YAT25DF081-MHN-TAT25DF081-UUN-TNotes:
1.The shipping carrier option code is not marked on the devices.2.Please contact Atmel for 11-ball dBGA package outline drawing.
Package Type
8S18MA111U1
8-lead, 0.150\" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-contact, 5 mm x 6 mm Thermally Enhanced Ultra Thin Dual Flat No Lead Package (UDFN)11-ball die Ball Grid Arrray (dBGA)
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14.3Ordering Code Detail – Wafer Level Options
AT25DF081–WBT11NAtmel DesignatorOperating VoltageN = 1.65V minimum (1.65V to 1.95V) Product FamilyDie/Wafer Backgrind Thickness20 = 20mils11 = 11milsDevice Density08 = 8-megabitDie/Wafer Carrier OptionT = Tape and reelInterface1 = SerialWafer Level OptionWD = Bare dieWB = Bumped die, Pb-Free14.4Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code
PackageBare DieBumped Die
Lead Finish
n/a
1.65V to 1.95V
Sn-Ag
66
Operating Voltage
fSCK (MHz)
Operation RangeIndustrial(-40°C to +85°C)
AT25DF081-WDT20NAT25DF081-WDT11NAT25DF081-WBT11NNotes:
1.Die/wafer carrier option code is not marked on devices.
2.Please contact Atmel for minimum order requirements for bare die and bumped die options.
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15.Packaging Information
15.1
8S1 – JEDEC SOIC
C1EE1NLØTOP VIEWebAA1END VIEWCOMMON DIMENSIONS(Unit of Measure = mm) SYMBOL A10.10–0.25MINNOMMAXNOTEDSIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.3/17/051150 E. Cheyenne Mtn. Blvd.Colorado Springs, CO 80906TITLE8S1, 8-lead (0.150\" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC)DRAWING NO.8S1REV. CR35
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15.28MA1 – UDFN
ECPin 1 IDDSIDE VIEWyTOP VIEWAK8A1E20.45Pin #1 Notch(0.20 R)(Option B)Option A1Pin #1 Chamfer(C 0.35)COMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE72D263e A A1 0.45 0.55 0.60 0.00 0.02 0.05 b 0.35 0.40 0.48 C 4.90 0.152 REF 5.00 5.1054 D bLBOTTOM VIEW D2 E E2 e L y K 3.80 4.00 4.205.90 3.20 0.50 0.00 0.20 6.00 3.40 1.270.60 0.756.103.60– 0.08– –4/15/08 Package Drawing Contact: packagedrawings@atmel.comTITLE8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No LeadPackage (UDFN)GPCYFGDRAWING NO.8MA1REV.D36
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16.Revision History
Revision Level – Release DateA – September 2007
HistoryInitial release
Changed part number ordering code to reflect NiPdAu lead finish
- Changed AT25DF081-SSU-1.8 to AT25DF081-SSH-1.8- Changed AT25DF081-MU-1.8 to AT25DF081-MH-1.8Added lead finish details to Ordering Information table
Changed description from “1.8-volt Only Serial Firmware DataFlash” to “1.65-volt Minimum SPI Serial Flash”Removed 8-ball dBGA
Changed Deep Power-Down current values
- Increased typical value from 4 µA to 8 µA
- Increased maximum value from 8 µA to 14 µAChanged typical Chip Erase time from 6 sec to 8 sec
Updated Ordering Information table and changed part numbering schemeChanged 8Y7 package to 8MA1 packageAdded 11-ball dBGA (WLCSP)
Updated Ordering Information table
Removed “Preliminary” status from the datasheet
B – October 2007
C – December 2007
D – January 2008E – August 2008
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Headquarters
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