Method for evaluating semiconductor device

专利名称：Method for evaluating semiconductor device发明人：Miyazono, Mitsuyoshi,Komatsu,

Shigekazu,Shinozaki, Dai,Kato,Masahiro,Yoshida, Atsushi

申请号：EP10172478.9申请日：20100811公开号：EP2290677A2公开日：20110302

专利附图：

摘要：A yield and productivity of a semiconductor module are improved. A sheethaving electrical conductivity is fixed to a main surface of a semiconductor substrate on

which a plurality of semiconductor devices having a surface structure and a rear surfaceelectrode are arranged. The semiconductor substrate is divided into semiconductor chipson a first support stage in the state where the sheet is fixed to its main surface. Theplurality of divided semiconductor chips are mounted on a second support stage via thesheet and further, the plurality of mounted semiconductor chips are continuouslysubjected to a dynamic characteristic test on the second support stage. The proposedsemiconductor device evaluation method permits a fissure growing and propagatingfrom a crack occurring in the dynamic characteristic test of the vertical semiconductordevices to be suppressed, and the yield and productivity of the semiconductor module tobe improved.

申请人：TOKYO ELECTRON LIMITED,Fuji Electric Systems Co., Ltd.

地址：3-1 Akasaka 5-chome Minato-ku Tokyo 107-6325 JP,11-2, Osaki 1-chomeShinagawa-ku Tokyo 141-0032 JP

国籍：JP,JP

代理机构：HOFFMANN EITLE

更多信息请下载全文后查看