Semiconductor integrated circuit device and layout

专利名称：Semiconductor integrated circuit device and

layout method of patterns for

semiconductor integrated circuit device

发明人：Sonohara, Hideo, c/o NEC Electronics

Corporation

申请号：EP03015320.9申请日：20030707公开号：EP1381085A2公开日：20040114

专利附图：

摘要：A semiconductor integrated circuit device includes macros (4) and area I/Os (3).

The macros are arranged in optional locations of a first empty area of a gate area (5) in acenter portion of a chip (1), respectively. Each of the area I/Os (3) contains a plurality ofarea I/O buffers, and is arranged in an optional location of a second empty area of a totalarea of the gate area and a buffer area in a circumferential portion of the chip. A firstmacro of the macros is connected with a specific one of the area I/Os. Here, the specificarea I/O may be related to the first macro and be arranged in relation to a location forthe first macro to be arranged.

申请人：NEC Electronics Corporation

地址：1753 Shimonumabe, Nakahara-ku Kawasaki, Kanagawa 211-8668 JP

国籍：JP

代理机构：Glawe. Delfs. Moll

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