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DDR PHY Interface (DFI) Specification

Memory Controller / PHY Interface Definition

Version 0.9

DENALI SOFTWARE, INC.

1850B Embarcadero Rd.Palo Alto, CA 94303Tel: (650) 461-7200Fax: (650) 461-7209

info@denali.comsales@denali.comwww.denali.com/supportwww.ememory.comAll Rights Reserved

Denali Software DDR PHY Interface (DFI) Specification1 of 23

Denali Software, Inc. Palo Alto, CA 94303

Revision NumberDateChange0.50.6

01 May 200605 May 2006

Initial Release.

Removed signal dfi_tsel.Corrected erroneous references.

0.7

16 May 2006

Corrected descriptions for unshifted enable signals.All enable and update signals made byte-enable.Read and write latency descriptions clarified.Timing diagrams modified and DDR1 diagrams added.

0.80.8.10.8.20.8.30.8.4

19 May 200622 May 200622 May 200624 May 200630 May 2006

Document Name Change.Legal Disclaimer Added.

Document generalized for any DDR controller.All signal names changed to dfi_ prefix.High-Frequency Diagram changed.Corrected erroneous Figure 10.

0.8.5

31 May 2006

Minor rewording.

Diagram descriptions enhanced.Formatting changes.

0.8.60.8.7

06 June 200623 June 2006

Modified destination control statement.Changed width description for dfi_data_disable dfi_dqs_disable and dfi_data_disable.Modified width of dfi_cke and dfi_rw_cke.

0.9

22 Aug 2006

Made changes from DFI WG July Meeting.Changed specification name.Corrected Figure 8.

Changed signal names/widths for update signals.Changed dfi_data_disable to be byte-wide.

Removed high-frequency and ecc signals in favor of making the memory signals multi-bit.Removed dfi_idle_drive_enable signal.

Proprietary Notice

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Denali Software DDR PHY Interface (DFI) Specification

No part of this document may be copied or reproduced in any form or by any means without prior written consent of Denali.

Denali makes no warranties with respect to this documentation and disclaims any implied

warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice. Denali assumes no responsibility for any errors that may appear in this document.

Except as may be explicitly set forth in such agreement, Denali does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy, or usefulness of the information contained in this document. Denali does not warrant that use of such information will not infringe any third party rights, nor does Denali assume any liability for damages or costs of any kind that may result from use of such information. RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in

subparagraphs (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

Destination Control Statement

All technical data contained in this product is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.Trademarks

Denali and the Denali logo are registered trademarks of Denali Software, Inc.

All other products or brand names mentioned are trademarks or registered trademarks of their respective holders.

Denali Software DDR PHY Interface (DFI) Specification3 of 23

Overview

1.0Overview

The DDR PHY Interface (DFI) is an interface protocol that will allow efficient connec-tivity to a DDR memory controller. The interface was designed to maximize perfor-mance, provide a rich set of features, and minimize the cost of integration of a DDR memory controller to a DDR PHY. The protocol defines the signals, timing, program-mability and functionality required for a PHY physical implementation to communicate with the memory controller. This interface does not encompass all of the features of the PHY, nor does it put any restrictions on how the PHY interfaces to the memory devices themselves. The user may utilize this information to develop a PHY, or to develop a PHY interface gasket which will translate between the DDR PHY Interface and an existing PHY implementation.

2.0Architecture

The DFI is specifically designed to interface with a DDR memory controller. All signals to and from the PHY are assumed synchronous in nature. There is only one clock

domain in which the memory controller will send signals to the PHY and receive signals from the PHY, and the memory controller will send all signals on the rising edge of this clock. Likewise, all signals from the PHY to the memory controller will be captured on the rising edge of this clock. It is assumed that this clock is source synchronous to the DRAM clock. The DFI also allows this clock to be source synchronous to 1/2 the DRAM frequency.

The PHY is ultimately responsible for all DRAM timing for reads and writes; PHY tim-ing information is conveyed to the memory controller through the DFI. The interface contains some flexibility in aligning write data with write commands and also indicating when read data will be returned. Read data must be presented to the memory controller for all read operations at a fixed time from when the memory controller issues a read data enable signal (dfi_rddata_en_unshifted). Write data will be presented to the PHY at a fixed time relative to the latency of the PHY. These time requirements mean that the PHY is also responsible for any data buffering due to the variance in system DRAM timing.

The DFI assumes that the PHY will be programmed and initialized prior to when the memory controller will begin communicating to the PHY or the DRAM devices. The PHY is only considered initialized for the DFI when it is able to accept any DRAM commands (initialization or read/write commands) from the memory controller and transfer them to the DRAMs. The validity of the data and timing for read and write operations, in terms of correct system timings to reliably write and read data, is not guaranteed at this time. The actual tuning and setting of the criteria for correct read and write data transactions is the combined responsibility of the memory controller and the PHY and should be handled at a level above what is represented in the DFI. Refer to Section4.1, “Initialization” for more details on this tuning.

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Denali Software DDR PHY Interface (DFI) Specification

Architecture

FIGURE 1.Block Diagram

dfi_wrdata_en

dfi_wrdata_en_unshifted

dfi_write_datadfi_write_dmdfi_rddata_en

dfi_rddata_en_unshifted

Write Data Interface

dfi_phy_write_latencyRead Data InterfaceDatapath Disable

Interface

dfi_read_data

dfi_phy_read_latency

dfi_data_disabledfi_dm_disable

dfi_addressdfi_bankdfi_cas_ndfi_ckedfi_cs_ndfi_odtdfi_ras_ndfi_we_n

dfi_address_disabledfi_bank_disabledfi_dram_clk_disable

dfi_update_cycledfi_update_start

Memory Control

Interface

Status Interface

dfi_init_complete

DDR Memory Controller

2.1Standard DFI Connection

PHY

In the default mode, the DFI data width is twice the width of the data interface between the PHY and the memory devices. It is assumed that the DFI is clocked by a source syn-chronous clock relative to the memory clock. For details on the read and write data interface protocols, refer to Section3.2, “Read Data Interface” and Section3.1, “Write Data Interface”.

The DFI clocks data on the rising edge of the clock. However, the memory interface clocks data on both the rising and the falling edges of the same clock. This clocking dif-ference creates a 2:1 ratio between the DFI and the memory interface. Inside the PHY, the 2N write data and mask pins must be routed to share N memory data and mask pins.

Denali Software DDR PHY Interface (DFI) Specification5 of 23

Architecture

FIGURE 2.Standard DFI Block Diagram

DFI

Address and Control Signals

PHY

Logic

Memory Interface

DRAM Address and Control Signals

dfi_write_data

pins

Logic

N DRAM data pins

dfi_read_data

pins

Logic

2.2High-Frequency DFI Connection

The DFI is defined to be configurable with respect to the frequency of the PHY and the memory controller. In the default mode, the memory controller, the DFI and the PHY operate at the same frequency. However, the DFI can also support a high-frequency con-figuration in which the PHY operates at twice, four or eight times the frequency of the memory controller.

In all cases, the DFI will still operate at the same clock frequency as the memory con-troller and will still clock data on the rising edge of the clock. However, the memory interface will be working at a multiple of the speed of the DFI, and will also be clocking data on both the rising and the falling edges of the clock. This clocking difference cre-ates a 4:1, 8:1 or 16:1 ratio between the DFI and the memory interface. Inside the PHY, the 4N, 8N or 16N write data and mask pins must be routed to share N memory data and mask pins.

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Denali Software DDR PHY Interface (DFI) Specification

Architecture

FIGURE 3.High-Frequency DFI Block Diagram

DFI

Address and Control Signals

PHY

Logic

Memory Interface

DRAM Address and Control Signals

4N, 8N or 16Ndfi_write_data

pins

Logic

N DRAM data pins

4N, 8N or 16Ndfi_read_data

pins

Logic

2.3Half Datapath Mode

The DFI has the programmable capability to support a memory datapath half as wide as the memory datapath of the PHY. If this situation is desired, the memory controller will drive pin disable signals to the PHY to indicate that the memory controller is in this mode. Only half of the pin disable signals of the DFI (dfi_data_disable,

dfi_dm_disable, dfi_dqs_disable) will be de-asserted, indicating which bytes of the DQ, DQS, and DM memory buses the memory controller is using. Only the data pins of the DFI whose disable signals are de-asserted will contain relevant data. Figure4, “Full Memory Datapath Usage” and Figure5, “Half Memory Datapath Usage” depict a typi-cal data pin mapping in the PHY for a 32-bit memory interface using the standard DFI configuration, with and without the half datapath option.

Denali Software DDR PHY Interface (DFI) Specification7 of 23

Architecture

FIGURE 4.Full Memory Datapath Usage

DFI

bits 7:0bits 15:8bits 23:16bits 31:24bits 39:32bits 47:40bits 55:48bits 63:56

Logic

PHY

Memory Interface

bits 7:0bits 15:8bits 23:16bits 31:24

FIGURE 5.Half Memory Datapath Usage

DFI

bits 7:0bits 15:8bits 23:16bits 31:24bits 39:32bits 47:40bits 55:48bits 63:56

The dotted lines represent unused signals. The disable signals associated with these

bits will be asserted.

Logic

PHY

Memory Interface

bits 7:0bits 15:8bits 23:16bits 31:24

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Denali Software DDR PHY Interface (DFI) Specification

Architecture

2.4ECC Configuration

The DFI will contain extra data, mask and data strobe pins when configured with the ECC option. In addition, extra disable pins will be included for ECC functionality to allow the ECC function to be disabled.

When the user wishes to disable ECC functionality, the memory controller can drive the associated bits of the dfi_data_disable and dfi_dm_disable signals high. This should trigger the PHY to consider the associated bits of the dfi_write_data and dfi_write_dm signals irrelevant and the memory controller should ignore these bits of the

dfi_read_data signals. Figure6, “ECC Used” and Figure7, “ECC Disabled” show the DFI/PHY/memory connection, with and without the ECC option enabled.

FIGURE 6.ECC Used

Memory Controller

Read/Write Data and Control Signals

DFIPHY

I/O Pad

Logic

I/O Pad

DRAM devices

ECC Generation and

Checking

Logic

I/O Pad

ECC Codes

Denali Software DDR PHY Interface (DFI) Specification9 of 23

Interface Signal Groups

FIGURE 7.ECC Disabled

Memory Controller

Read/Write Data and Control Signals

DFIPHY

I/O Pad

Logic

I/O Pad

DRAM devices

ECC Generation and

Checking

Logic

I/O Pad

The dotted lines represent unused signals. The disable signals associated with these

pins will be asserted.

3.0Interface Signal Groups

The DFI is subdivided into several signal groups for the types of data that must be trans-ferred between the memory controller and the PHY. In many cases, the width of a signal is dependent on the width of the buses configured in the DDR memory controller. Some signals are feature-dependent and are noted by the feature.3.1Write Data Interface

The write data interface supplies write data and write data enable signals to the PHY. The timing relationship between when the write data is available and the enable signals are asserted to when the write command is sent from the DFI is programmable. Write data can be sent on the cycle after the write command, or it can be delayed to account for command and data latency in the PHY and CAS latency in certain DRAM devices. An unshifted version of the enable signal will be sent with the write command, and a second enable signal will be sent on the cycle before the write data. The write data enable signals are valid for the expected length of contiguous write data sent to the DRAM. The signals in the write data interface are listed in Table1.

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Denali Software DDR PHY Interface (DFI) Specification

Interface Signal Groups

When ECC is configured on the memory controller and is being used by the memory devices, ECC signals are also sent with the write data as extensions to the dfi_write_data and dfi_write_dm buses.

TABLE 1.

Signal

dfi_phy_write_latency

Write Data SignalsFromPHY

ToDDRMemoryController

WidthPHY WRLATWIDTH

Description

Specifies the difference between the command-com-mand delay (in registered stages) and the data-data delay (in registered stages) from the DFI to the DRAM interface. In general, the data delay will be greater and the value of this signal must be a positive number. This signal must be static when the dfi_init_complete sig-nal is set.

Write data, data strobe, and data mask enable signal. This signal is asserted one cycle before the data is sent on the DFI interface and is adjusted for CAS latency and registered DIMM timing. This signal, once asserted, will remain asserted for the number of con-tiguous cycles of write data intended for the DRAM.There is a single enable signal bit for each byte of the DRAM data. The bits will all be identical in value; however, the memory controller must output these sig-nals from separate flip-flops.

dfi_wrdata_enDDRMemoryController

PHYDRAM DATAWIDTH / 8

dfi_wrdata_en_unshiftedDDRMemoryController

PHYDRAM DATAWIDTH / 8

Same as the dfi_wrdata_en signal, with the exception that this signal is asserted on the same cycles as the write command on the DFI and not shifted for CAS latency or registered DIMM. This signal is intended to be used in the DQS preamble and I/O enable/disable circuit in the PHY.

There is a single enable signal bit for each byte of the DRAM data. The bits will all be identical in value; however, the memory controller must output these sig-nals from separate flip-flops.

dfi_write_dataDDRMemoryController

PHY2 or 4 times theDRAM DATAWIDTH

Write data signal. Write data timing is adjusted for reg-istered DIMM support.

dfi_write_dmDDRMemoryController

PHY2 or 4 times theDRAM DMWIDTH

Write data byte mask signal. The timing is the same as for the write data.

3.2Read Data Interface

Read data is always returned to the memory controller in a fixed number of clocks rela-tive to the read command. The read data accounts for CAS latency, Registered DIMM timing, and flight time. The read data enable control signals provide the necessary tim-ing information. The signals in the read data interface are listed in Table2.

Denali Software DDR PHY Interface (DFI) Specification

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Interface Signal Groups

When ECC is configured on the memory controller and is being used by the memory devices, ECC signals are also sent with the read data as extensions to the dfi_read_data

bus.

TABLE 2.

Signal

dfi_phy_read_latency

Read Data SignalsFromPHY

ToDDRMemoryController

Width5 bitsMaximum 32 cycles of latency in the

PHY

Description

Number of cycles from when the read command has been registered in the PHY to when valid read data on the dfi_read_data signal has been registered in the memory controller. It is mandatory that the PHY always maintains this latency for all read commands from the memory controller. This signal must be static when the dfi_init_complete signal is set.

Read data enable signal. This signal is asserted after the read command and indicates the width of the data transfer on the DFI (i.e. Asserted 2 clocks for BL-4). This signal is adjusted for CAS latency and registered DIMM timing, but not for any PHY or board delays.There is a single enable signal bit for each byte of the DRAM data. The bits will all be identical in value; however, the memory controller must output these sig-nals from separate flip-flops.

dfi_rddata_enDDRMemoryController

PHYDRAM DATAWIDTH / 8

dfi_rddata_en_unshiftedDDRMemoryController

PHYDRAM DATAWIDTH / 8

Same as the dfi_rddata_en signal, with the exception that this signal is not delayed for CAS latency or regis-tered DIMM. This signal is included for any DQS con-ditioning prior to the delivery of the DRAM data for the read command. This signal is asserted on the same cycle as the associated read command and will remain high for the number of contiguous cycles of read data expected by the memory controller.

There is a single enable signal bit for each byte of the DRAM data. The bits will all be identical in value; however, the memory controller must output these sig-nals from separate flip-flops.

dfi_read_dataPHYDDRMemoryController

2 or 4 times theDRAM DATAWIDTH

Read data signal.

3.3Data Path Disable Interface

There are circumstances where certain or all of the datapath signals to the DRAM must be disabled. The memory controller will assert these datapath disable signals to indicate that these pins are either not connected to the external DRAM interface or no longer active in the system.

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Denali Software DDR PHY Interface (DFI) Specification

Interface Signal Groups

The DFI provides individual disable signals for each data path signal. The signals in the data path disable interface are listed in Table3.

When ECC is configured on the memory controller and is being used by the memory devices, ECC signals are also transferred with data on the read or write data buses. However, there are potential scenarios when these signals may need to be disabled, for part or all of the data path. The DFI disable buses include disables for the ECC signals as well.

TABLE 3.

Signaldfi_data_disable

FromDDRMemoryController

dfi_dm_disable

DDRMemoryController

Data Path Disable SignalsToPHY

WidthDFI DATAWIDTH / 8

Description

Active bits indicate that the associated DQ byte on the DRAM inter-face is not active and should be disabled. For datapaths that are not byte-aligned, the most significant bit of the datapath will relate to the partial byte.

Active bits indicate that the associated DM pin on the DRAM inter-face is not active and should be disabled.

PHYDFI DMWIDTH

3.4Memory Control Interface

The memory controller includes signals to drive the memory address, command, and control signals. These signals will be passed through the DFI, and the PHY may need to add register delays to these signals for correct timing. The PHY may also require an Address, Command, and Control signal macro to improve the physical timing of these signals. These signals are used in both data and non-data transactions. The signals in the memory control interface are listed in Table4.

It is possible that the PHY operates at a multiple of the frequency of the memory con-troller. If this is the case, then the memory controller will need to send additional infor-mation to the PHY on each clock cycle. For these instances, each of the memory control signals are replicated as needed.

TABLE 4.

Signaldfi_address

FromDDRMemoryController

dfi_bank

DDRMemoryController

Memory Control SignalsToPHY

WidthADDRESS WIDTH(or a multiple of the ADDRESS WIDTH for higher frequency PHYs)

PHY

BANK WIDTH(or a multiple of the BANK WIDTH for higher

frequency PHYs)

Memory bank address.Memory address.

Description

Denali Software DDR PHY Interface (DFI) Specification13 of 23

Interface Signal Groups

TABLE 4.

Signaldfi_cas_n

FromDDRMemoryController

dfi_cke

DDRMemoryController

Memory Control SignalsToPHY

Width1 bit

(or multi-bit for higher frequency PHYs)

PHY

NUM OFCHIP SELECTS(or a multiple of the NUMBER OF CHIP SELECTS for higher fre-quency PHYs)

PHY

NUM OFCHIP SELECTS(or a multiple of the NUMBER OF CHIP SELECTS for higher fre-quency PHYs)

PHY

NUM OFCHIP SELECTS(or a multiple of the NUMBER OF CHIP SELECTS for higher fre-quency PHYs)

PHY

1 bit

(or multi-bit for higher frequency PHYs)

PHY

1 bit

(or multi-bit for higher frequency PHYs)

Memory write enable.Memory row address strobe.

Memory on-die termination control signal.Memory chip selects.Memory clock enable.

Description

Memory column address strobe.

dfi_cs_nDDRMemoryController

dfi_odtDDRMemoryController

dfi_ras_nDDRMemoryController

dfi_we_nDDRMemoryController

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Denali Software DDR PHY Interface (DFI) Specification

Functional Use

3.5Status Interface

A DDR memory controller requires information on the status of the PHY to know when signals may be modified as well as when the PHY clock is operational. The signals in the status interface are listed in Table5.

TABLE 5.

Signaldfi_address_disable

FromDDR

Status Interface Signals

ToPHY

WidthMAX NUMBEROF ADDRESS PINS

PHY

NUMBER OFBANK PINS

PHY

NUMBER OFCHIP SELECTS

DDRMemoryController

1 bit

Description

Active bits indicate that the associated address pin on the DRAM interface is not active and should be disabled.

Active bits indicate that the associated bank pin on the DRAM interface is not active and should be dis-abled.

Disables the clock to the DRAM devices. Used for power savings.

MemoryController

dfi_bank_disable

DDRMemoryController

dfi_dram_clk_disable

DDRMemoryController

dfi_init_complete

PHY

PHY initialization complete signal. This signal indicates that the PHY is initialized and ready to accept DRAM commands for the memory control-ler.

Indicates the number of cycles that the memory controller will not issue read or write commands to the PHY. This allows the PHY to perform updates without potentially missing an incoming command.Indicates that the memory controller has entered idle behavior. Following this pulse, the memory controller will not issue read or write commands to the PHY for the number of cycles set in the dfi_update_cycles signal.

dfi_update_cyclesDDRMemoryController

PHY1 byte

dfi_update_startDDRMemoryController

PHY1 bit

4.0Functional Use

4.1Initialization

The initialization sequence for the DDR memory controller and PHY combination includes the following events:

••••

Reset

PHY Register Programming

Memory Controller Register ProgrammingDRAM Initialization Sequence

Denali Software DDR PHY Interface (DFI) Specification15 of 23

Functional Use

•Read/Write Strobe Tuning (Optional)

The DDR memory controller and the PHY should both be held in reset until the power and ground levels are stable. Once the system is stable, reset must be de-asserted syn-chronous to the memory controller clock. Any additional clocks and resets required by the PHY exist in the PHY time domain, and the PHY should handle these as well as any additional initialization requirements.

The memory controller requires a signal from the PHY indicating that the PHY is fully initialized. This signal should be connected to the dfi_init_complete signal of the DFI. When this signal is asserted, the memory controller assumes that the PHY is able to transfer any DRAM commands to the DRAM devices, and is able to send write data and strobes to the DRAM devices. The actual timing of the data and strobes may or may not completely match all DRAM timing protocols or give maximum margin to the system. The memory controller and the PHY timing can be further tuned by the system to ensure that read and write data is transferred from/to the DRAMs without error using the

dfi_phy_read_latency and dfi_phy_write_latency signals. Whenever the latency must be changed, the PHY must de-assert the dfi_init_complete signal and then re-assert the signal when the correct value(s) is/are stable on the dfi_phy_write_latency and/or dfi_phy_read_latency signal(s).4.2Write Transactions

The write transaction portion of the DFI includes the write data (dfi_write_data), write data mask (dfi_write_dm), and write data enable (dfi_wrdata_en,

dfi_wrdata_en_unshifted) signals. If configured within the DDR memory controller, and being used, then the ECC data and mask information is also transferred on the write data and write mask buses.

All signals sent from the DDR memory controller to the DFI are driven from a register.The dfi_wrdata_en and dfi_wrdata_en_unshifted signals will be asserted for the number of clocks required for the write data transfer. The dfi_wrdata_en signal

includes adjustments from the dfi_phy_write_latency from the PHY and will be active one cycle before the write data is sent to the PHY. The dfi_wrdata_en_unshifted signal is always asserted on the same cycle as the write command.

The DFI accounts for timing differences between DDR1 and DDR2 devices for the time from a write command to when data is received. For DDR1 devices, write data is driven on the clock following the command. For DDR2 devices, write data will be delayed, accounting for CAS latency and the dfi_phy_write_latency defined by the PHY.The dfi_phy_write_latency is defined as the difference in register stages for the com-mand and data between the DFI and the DRAM interface. The command delay is the number of register stages between the DFI command input and the command output to the DRAM interface. The data delay is the number of register stages between the DFI data input and the data output to the DRAM devices. The difference between the two delays is the correct dfi_phy_write_latency value. The data delay will always be

greater than or equal to the command delay, and the latency must be a positive number.

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Denali Software DDR PHY Interface (DFI) Specification

Functional Use

For the back-to-back write examples shown in Figure8, Figure9 and Figure10, the command and data delays are identical, so the dfi_phy_write_latency signal should be driven with a zero for this PHY. For the non-sequential write example shown in

Figure11, the data delay is longer than the command delay by one registered stage, so the dfi_phy_write_latency signal should be driven with a 0x1 for this PHY.

The memory controller will utilize this information to delay the data relative to the com-mand appropriately, eliminating the need for extra registering in the PHY.

FIGURE 8.

DFI Signals

clk

command to the DFIdfi_write_datadfi_wrdata_en

dfi_wrdata_en_unshifted

Memory Signals

CLK

command to memory

DQDQS

Back-to-Back Writes for a DDR1 device with BL=4 and Read CAS Latency=5

WRD01WRD23D45D67WRWR01234567Cmd DelayData Delay

Data Delay = Cmd Delaydfi_phy_write_lat= 0x0

FIGURE 9.

DFI Signals

clk

command to the DFIdfi_write_datadfi_wrdata_en

dfi_wrdata_en_unshifted

Memory Signals

CLK

command to memory

DQDQS

Back-to-Back Writes for a DDR2 device with BL=4 and Read CAS Latency=5

WRWRD01D23D45D67WRWR01234567Cmd DelayData DelayData Delay = Cmd Delaydfi_phy_write_lat= 0x0

Denali Software DDR PHY Interface (DFI) Specification17 of 23

Functional Use

FIGURE 10.

DFI Signals

clk

command to the DFIdfi_write_datadfi_wrdata_en

dfi_wrdata_en_unshifted

Memory Signals

CLK

command to memory

DQDQS

Non-Sequential Writes for a DDR1 device with BL=4 and Read CAS Latency=5

WRD01D23WRD45D67WR0123WR4567Cmd DelayData DelayData Delay = Cmd Delaydfi_phy_write_lat= 0x0

FIGURE 11.

DFI Signals

clk

command to the DFIdfi_write_datadfi_wrdata_en

dfi_wrdata_en_unshifted

Memory Signals

CLK

command to memory

DQDQS

Non-Sequential Writes for a DDR2 device with BL=4 and Read CAS Latency=6

WRWRD01D23D45D67WRWR01234567Cmd DelayData Delay

Data Delay - Cmd Delay = 1dfi_phy_write_laten= 0x1

4.3Read Transactions

The read transaction portion of the DFI includes the read data (dfi_read_data) and read data enable (dfi_rddata_en, dfi_rddata_en_unshifted) signals. If configured within the DDR memory controller, and being used, then the ECC information is also trans-ferred on the read data bus.

For the DDR memory controller, the timing from when a read command is registered in the PHY to when the returned read data is registered in the memory controller must be a constant. This constant must be provided to the memory controller on the

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Denali Software DDR PHY Interface (DFI) Specification

Functional Use

dfi_phy_read_latency signal. With this information, the memory controller will be able to accurately receive read data from the PHY. The examples shown in Figure12, Figure13 and Figure14 represent systems with different numbers of register stages between command and data, and therefore their dfi_phy_read_latency values will be different.

The fixed delay time requirement of the memory controller, and the absence of a valid read data signal, means that the PHY must contain an elasticity buffer to absorb differ-ences in the arrival time of read data relative to the core clock.

The dfi_rddata_en and dfi_rddata_en_unshifted signals set the relative timing of the expected data from the read command and the data width. These signals indicate how many active read data cycles the memory controller is expecting. For DDR1 devices, this signal can be of any duration regardless of the burst length programmed into the DRAM devices. For DDR2 devices, this signal will always be multiples of 2 cycles (burst of 4). The dfi_rddata_en_unshifted signal does not compensate for any delays and is aligned with the read command sent on the DFI. The dfi_rddata_en signal accounts for CAS latency and DIMM registering in the DRAM devices.

In Figure12, the dfi_rddata_en and dfi_rddata_en_unshifted signals are each

asserted for two cycles to inform the PHY that the memory controller is expecting two user words of data. The dfi_rddata_en signal is sent four cycles after the command to account for the CAS latency.

Figure13 and Figure14 show interrupted read commands. In both cases, the

dfi_rddata_en and dfi_rddata_en_unshifted signals should be asserted for 4 cycles for each transaction. However, since the first read is interrupted in both cases, the result-ing enable signals are asserted for a portion of the first transaction and the complete sec-ond transaction.

FIGURE 12.

clk

command to the DFIdfi_rddata_en

dfi_rddata_en_unshifted

dfi_read_data

DDR1 or DDR2 Read Transaction with BL=4, CAS Latency=4 and Non-Registered DIMM

RDD01CAS Latency

D23dfi_phy_read_latency= 0x9

Denali Software DDR PHY Interface (DFI) Specification19 of 23

Functional Use

FIGURE 13.

clk

command to the DFIdfi_rddata_en

dfi_rddata_en_unshifted

dfi_read_data

DDR1 Burst Read Transaction with BL=8, CAS Latency=3 and Non-Registered DIMM

RD1RD2D1CAS Latency

D2D2D2D2dfi_phy_read_latency= 0x7

FIGURE 14.

clk

command to the DFIdfi_rddata_en

dfi_rddata_en_unshifted

dfi_read_data

DDR2 Interrupted Burst Read Transaction with BL=8, CAS Latency=2 and Registered DIMM

RD1RD2D1CAS LatencyDIMM Delay

D1D2D2D2D2dfi_phy_read_latency= 0x6

4.4High-Frequency Transactions

In a high-frequency mode, the DFI uses multiple pins to convey address and control information to the PHY. Refer to Table4, “Memory Control Signals” for more informa-tion on these signals.

The memory DFI datapath width to the memory interface data width is at least 2:1. With a high-frequency configuration, the ratio could be 4:1, 8:1 or 16:1. This means that if the DRAM interface is 32 bits, the DFI data interface will be 128 bits, 256 bits, or 512 bits wide. For such configurations, the memory control signals are vectored, allowing additional data to be sent between the memory controller and the PHY on each clock edge.

In order to support even and odd CAS latencies of the DRAM devices, the PHY must send write data on the correct fast clock cycle. The DFI will send each write data word assuming even write CAS latencies. Therefore, if the DRAMs are programmed for an odd write CAS latency, then the PHY is responsible for delaying the sending of write data one fast clock cycle.

Figure15 shows a situation with a PHY operating at twice the frequency of the memory controller. It is assumed that the [0] signals on the memory control interface are used for non-data transactions (bank opens/closes) and the [1] signals are used for data transac-

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Denali Software DDR PHY Interface (DFI) Specification

Functional Use

tions. With this assumption, the write commands are CmdB and CmdD, and therefore the Command Delay is shown relative to when CmdB is sent to the memory devices. The DQ data output is shown for both a Read CAS latency of 5 or 6. The command and data would be sent through the DFI on the same clocks as shown for either Read CAS latency value. The PHY must add the extra delay to the DQ for Read CAS latency 6.

FIGURE 15.

DFI SignalsDFIclk

mem ctrl signals [0]mem ctrl signals [1]dfi_write_datadfi_wrdata_en

dfi_wrdata_en_unshifted

PHY SignalsPHY clockMemory SignalsMemory Control SignalsDQ (Read CAS Latency 5)DQ (Read CAS Latency 6)

DDR2 Double-Frequency Write with BL=4 and Read CAS Latency=5 or 6

CmdACmdBCmdCCmdDSTUVWXYZDFI clock to PHY clock latency dependent on PHY architectureCmdACmdBCmdCCmdDSUTVWYXZSUTVWYXZCmd Delay

Data Delay

Data Delay = Cmd Delaydfi_phy_write_latency= 0x0

4.5Half Datapath Mode Usage

When the half datapath mode is configured in the memory controller, only half of the write data pins from the memory controller to the PHY will contain valid data, and the memory controller will expect the same data format for read data.

The memory controller will drive pin disable signals to the PHY to indicate that the memory controller is in this mode. These pin disable signals of the DFI

(dfi_data_disable, dfi_dm_disable, dfi_dqs_disable) will be active for half of the DQ, DQS, and DM pins of the DRAM interface. Pins of the memory interface with active pin disable signals will not be used to convey information to the memory devices.If the PHY maintains the pin mapping as shown, then read and write data will be accu-rately routed to the appropriate pins and the disable signals can be used to disable the unused pads. The PHY is not required to maintain this pin ordering; however, the mem-ory controller will expect the data in the manner specified in the disable signals.Note that only half of the incoming data pins contain valid data and therefore, the PHY is free to remap these signals to any pins on its memory interface. If the mapping is modified, then read data must be re-mapped to the appropriate pins for proper commu-nication.

Denali Software DDR PHY Interface (DFI) Specification21 of 23

Functional Use

4.5.1Configuration of Used Pins

There are multiple possible configuration options for the data using half datapath mode. Three most common examples are as follows:

•Upper half of the memory pins are used.•Lower half of the memory pins are used.•The middle memory pins are used.

As an example, assume that the DFI is configured for a 32 bit datapath, but the half datapath mode is being used. 16 bits of valid data will be contained in the incoming data stream, depending on the pin configuration being used.

If ECC is configured on the DFI, the ECC pins follow the same behavior and only half of the dfi_write_data pins that correspond to ECC information will send valid data to the PHY.

MIKE: Consider the system with a 32-bit memory interface, in half-datapath (lower half) mode, with a 16-bit ECC (6 bits check code). Since ECC is now part of the data bus, then would the memory pins used be [34:32] and [15:0] and then the disable signal be 0x38ffff0000ffff0000????

TABLE 6: Memory Pin Usage Example

Memory Pins Used

DFI Pins Used

3163

032

Data Disable Signal0x0000ffff0000ffff

Upper Half

Lower Half

03163

032

0xffff0000ffff0000

Middle

03163

032

0x00ffff0000ffff00

4.5.2Transferring Data

The half datapath mode under-utilizes the memory controller and therefore, two cycles are required to transfer the same amount of data when using half datapath mode. For example, if the DFI width was 64-bits, then the DFI could transfer a 64-bit word

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Denali Software DDR PHY Interface (DFI) Specification

Functional Use

0xddddccccbbbbaaaa through the DFI in a single cycle. However, when using half data-path mode, the DFI would require two cycles and the data would need to be mapped to the relevant bits. If the lower half of the memory pins were being used, then the same data would be transferred in the following manner:Cycle 1: 0x0000bbbb0000aaaaCycle 2: 0x0000dddd0000cccc4.6Disabling ECC

If the memory controller is configured to generate ECC data on write transactions and verify ECC data on read transactions, then additional memory is required to hold this data. However, there are situations in which the ECC generation/checking may need to be disabled. Two situations where this may be required are the following:

•ECC signals are present, but ECC functions are disabled in the memory controller.•When ECC is not available. While the memory controller may support ECC func-tionality, the memory system being used may not do so.

The DFI accounts for these situations by providing data path disables for the ECC func-tions. If ECC is disabled in the memory controller, then the associated bits of the dfi_data_disable and dfi_dm_disable signals will be driven to a fixed state and no ECC checking or generating will occur. If the half datapath mode is being used, then the bits of the ECC bus that are not being used will have their associated disable bits driven high.

4.7Status Behavior

The DFI includes status signals to communicate between the PHY and the memory con-troller.

4.7.1

Slave Update

During normal operation, the PHY may occasionally need to update internal registers or outputs or perform other PHY-specific functions. The functions require several clock cycles, and if initiated arbitrarily may cause the PHY to miss memory controller com-mands. The dfi_update_start and dfi_update_cycles signals are provided for this pur-pose. When the memory controller detects an idle time between transactions, it will inform the PHY of an idle time by pulsing the dfi_update_start signal. The PHY will then be free to perform any internal operations necessary, with the guarantee that the memory controller will not issue any commands on the DFI for at least the number of cycles specified in the dfi_update_cycles signal.

Denali Software DDR PHY Interface (DFI) Specification23 of 23

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