HIGH SPEED, LOW CURRENT CONSUMPTION FIFO CIRCUIT

专利名称：HIGH SPEED, LOW CURRENT

CONSUMPTION FIFO CIRCUIT

发明人：Hiroshi SHIROTA申请号：US11948568申请日：20071130

公开号：US20080091869A1公开日：20080417

专利附图：

摘要：A FIFO circuit includes a write counter circuit, a memory circuit, a read countercircuit and a selector circuit. The write counter circuit counts a write clock signal during avalid period of input data, and outputs a write counter value. The memory circuit stores

the input data in response to the write counter value. The read counter circuit counts aread clock signal when a decision is made that the memory circuit includes data that hasnot yet been read out, and outputs a read counter value. The read selector circuit readsdata from the memory circuit in response to the read counter value. A small scale FIFOcircuit can be obtained.

申请人：Hiroshi SHIROTA

地址：Tokyo JP

国籍：JP

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